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mips-and-upower-processors's Introduction

A1

Building a simulator for the uPower ISA using Python

A3-A4

Integrating Verilog modules to build datapaths for MIPS and uPower ISAs

Team (alphabetical): Niranjan S Yadiyala (181CO136) Rajath C Aralikatti (181CO241) Shruthan R (181CO250) Varun NR (181CO134)

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