A simple MIPS processor implemented using Verilog capable of supporting basic I,J and R type instructions. Built using Xilinx Vivado 2019.1
separate data and instruction memory
256*4= 1024 bytes = 1KB consisting of 256 32-bit registers.
Addressing is word-aligned.
1024 bytes = 1 KB consisting of 1024 8-bit registers.
Addressing is byte-aligned. Each instruction is of 4 bytes.
◦ADD
◦SUB
◦AND
◦OR
◦NOR
◦XOR
◦SLT
◦SLTU
◦SRL
◦SRLV
◦SRA
◦SRAV
◦SLL
◦SLLV
◦ADDI
◦ORI
◦ANDI
◦XORI
◦SLTI
◦SLTIU
◦BEQ
◦BNE
◦BLTZ
◦BGTZ
◦LW
◦SW
◦J
◦JAL
Certain R-type instructions haven’t been implemented such as NAND, XNOR etc. Also, more complex instructions like MUL, DIV, move operations and trap instructions cannot be run on our simple processor.
Clock period = 100 ns = 10^(-8)s
So, clock frequency = 10^8 Hz = 100 MHz
A register between the fetch and the decode/exe stage stores the fetched instruction.
Branch involves a No-Op instruction after the branch statement as due to the 2-stage pipeline, in the same clock cycle in which the Branch instruction is executed, the No-Op instruction is fetched and it doesn’t affect the overall running of the processor.
N+1/N where N is the no. Of instructions to be executed.
CPI tends to 1 as N becomes very large.
Sum of n numbers
HCF of 2 numbers
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