Comments (2)
Hey Zach!
Thanks for submitting this. I agree that the tool should have provided a better error message here. I usually add assertions to trap conditions that shouldn't ever happen regardless of user input. It looks like you were able to stir up a rare edge-case I didn't expect.
Analyzing this a bit more, the specific conflict that is happening is that an unqualified hw=w
policy along with singlepulse
describes a field that doesn't quite make sense:
hw=w
(orrw
in your case) without a load-enable fromwe = true
implies that hardware will update the value of the field's storage element every clock cycle unconditionally.singlepulse = true
dictates the field will be cleared back to 0 at the next clock cycle, also unconditionally.
This combination of properties is impossible to satisfy, so it results in an error. The SystemRDL spec doesn't explicitly specify all the possible conflicts you could create, likely because there would be far too many to enumerate in a document 😄 .
I'll definitely fix the error message so that it is more informative.
Thanks again for submitting this!
from peakrdl-regblock.
Related Issues (20)
- Interface data width vs register width vs access width HOT 1
- Unaligned external addressable components
- Clock gating support HOT 4
- More optimized readback stage RTL generation HOT 3
- Put pragmas around assertions HOT 2
- Parity on R/W registers HOT 2
- Fine-grained access rights HOT 2
- [FEATURE] External register fields HOT 1
- [BUG] memory size is not calulated correctly HOT 4
- External registers packed struct HOT 1
- [FEATURE] Parameters in regblock package
- [BUG] Genus unsynthesizable error on rising/falling edge interrupt field
- Request to change from typdef enum int to typedef enum logic to resolve Lint Issues. HOT 5
- Casting For-Loop Iterator to Match Address Width in Decoding Logic
- SW = rw, HW = rw behavior seems incorrect HOT 3
- Files generated by this project do not work with Verilator HOT 3
- Timing of swmod seems 1 cycle too early HOT 2
- External mem state machine gets confused by rd_ack that may result from READ_FIRST BRAMs HOT 3
- hwset on multibit field HOT 5
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