Comments (3)
paul-demo
commented on September 2, 2024
It could be that it just can't be at the top level of a verilator build, which actually isn't a big limitation. Once I get a wrapper module assembled, I'll try it out with the unpacked structs.
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amykyta3
commented on September 2, 2024
I haven't done any unit-testing with Verilator yet, but from what I understand it should work. There are a few limitations with Verilator that prevent me from also using in unit-tests due to testbench constructs that I use (#41), but it looks like the developers are pretty close to expanding support needed for that too.
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paul-demo
commented on September 2, 2024
Hooray! It seems to work fine leaving them as unpacked structs as long as you are not using the generated file as the top level (which I was doing originally, just to simulate it to see what artifacts this project produces).
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Related Issues (20)
- Interface data width vs register width vs access width HOT 1
- Unaligned external addressable components
- Clock gating support HOT 4
- More optimized readback stage RTL generation HOT 3
- Put pragmas around assertions HOT 2
- Parity on R/W registers HOT 2
- Fine-grained access rights HOT 2
- [FEATURE] External register fields HOT 1
- [BUG] memory size is not calulated correctly HOT 4
- External registers packed struct HOT 1
- [FEATURE] Parameters in regblock package
- [BUG] Genus unsynthesizable error on rising/falling edge interrupt field
- Saturating counters perform inequality check twice in generated logic
- Casting For-Loop Iterator to Match Address Width in Decoding Logic
- unconditional is None # Can only have one unconditional assignment per field HOT 2
- SW = rw, HW = rw behavior seems incorrect HOT 3
- Timing of swmod seems 1 cycle too early HOT 2
- External mem state machine gets confused by rd_ack that may result from READ_FIRST BRAMs HOT 3
- hwset on multibit field HOT 5
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