Final project for 6.2050 Fall 2022 by Pleng Chomphoochan ([email protected]) and Dillon DuPont ([email protected]).
The writeup can be accessed at writeup/fpga_final_writeup.pdf
(view on Github or download).
We present a design for a hardware-based graphics pipeline that uses the ray marcher algorithm to render infinitely large scenes on an FPGA. Our design utilizes approximately 0.2 MB of Block RAM on a Nexys4 DDR Artix-7 FPGA board to render a 400 by 300 grayscale image at a rate of 30-60 frames per second. We implement, test, and evaluate the performance of our design, and discuss potential improvements.