trabucayre / openfpgaloader Goto Github PK

Hi, When trying to upload the code to the device (tang Nano) with:
openFPGALoader -m -b tangnano led_prj.fs
(the .fs file was generated with the vendor tools and must be good, since its the default example)

With this, I get in return:
unable to open ftdi device: -3 (device not found)

Furthermore, I connected the device via USB and the cable is good, since I tested it with other devices and works in data transfer mode.

When I do lsusb, also the device does not appear. Any idea of whats going wrong?

Best regards, and thank you.

Paulo

On ULX3S we are using FT231X chip so I do not know if there is possibility to add that one....

www.ftdichip.com/Documents/DataSheets/ICs/DS_FT231X.pdf

All tools we are using are mostly described here:

https://github.com/emard/ulx3s-bin

Loading bitstream works on Mac OS X, but loader is reporting detach error 12:

./openFPGALoader -b ulx3s ~/fpga/saxon-45f.bit
Open file /Users/user/fpga/saxon-45f.bit DONE
Parse file DONE
Enable configuration: DONE
SRAM erase: DONE
Loading: [==================================================] 100.000000%
Done
Disable configuration: DONE
detach error -12

Same happens with administrator/root privileges:

sudo ./openFPGALoader -b ulx3s ~/fpga/saxon-45f.bit
Open file /Users/user/fpga/saxon-45f.bit DONE
Parse file DONE
Enable configuration: DONE
SRAM erase: DONE
Loading: [==================================================] 100.000000%
Done
Disable configuration: DONE
detach error -12

I don't see any side effects except it is annoying to see error above.

Something to investigate or to ignore the error.

Maybe it should be more internationnal with English message:

openFPGALoader -m -b tangnano ./lcd_pjt/impl/pnr/lcd_pjt.fs
erreur de write
erreur de write
erreur de write
erreur de write
erreur de write

I'm using a LCMX02-640HC for a project. My main machine is a Macbook, but I run Lattice Diamond under a Windows VM. I'd love to be able to program the chip using the Mac without booting the VM.

I added the following line to part.hpp
{0x012b9043, {"lattice", "MachXO2", "LCMXO2-640HC"}},

That seems to have made it work. I can't fully test the part at the moment, but it acts like the process is completing and the chip is probably working (very simple test).

Also, the only other main hurdle I had to overcome to get it to compile was to install libftdi1. brew didn't have it, but MacPorts did.

sudo port install libftdi1
After that, I could configure and build it. I could not build a static executable, but dynamic linking seems fine.

Also, FYI, there are a few more parts listed here, in case you care.
https://www.retrotronics.org/svn/jride/trunk/machxo2_internal.h

The DE10 nano has a built in USB Blaster, VID:PID 09fb:6810.

Running openfpgaloader -c usb-blaster lut.rbf

fails with:

write to ram
unable to open ftdi device: -3 (device not found)
Error: Failed to claim cable

Is this board supposed to work (the various USB blaster versions are a bit unclear?)

Feature wish: a short note in readme on how to build
static executable, independent from shared libraries.

It could increases portability of compiled executable
accross various linux distro's.

When building on Ubuntu 20.04 I encounter the following error:

...
[ 95%] Building CXX object CMakeFiles/openFPGALoader.dir/src/bitparser.cpp.o
[100%] Linking CXX executable openFPGALoader
/usr/bin/ld: cannot find -ludev
/usr/bin/ld: cannot find -ludev
collect2: error: ld returned 1 exit status

My build incantations are:

1. cd build ; cmake -DBUILD_STATIC=ON -DCMAKE_INSTALL_PREFIX=/usr ../
2. make -j$(nproc)

Any ideas how to solve this?

Any chance you could add support for the FT232H, like the Adafruit breakout board? I understand they only have a single channel, unlike the FT2232, but they’re cheap and ubiquitous. I specifically want to use it with my ECP5 evaluation board.

Hey, would it be possible to add a release so that I can package this in the Arch Linux repos?

Hi,
I've added the following line to ../src/part.hpp:

{0x037c4093, {"xilinx", "spartan7", "xc7s25csga225"}},

and successfully loaded a bitfile inside the aforementioned spartan7. Maybe it could be good for others to add this to the main branch.

Best,
dbellix

I'm trying to program the Tang Nano but it gets stuck at 99%

$ openFPGALoader -b tangnano ../pack.fs 
Parse ../pack.fs: 
00
Done
erase SRAM Done
Flash SRAM: [==================================================] 99.902534%^C

My git reflog looks as follows:

a220226 (HEAD -> master, origin/master, origin/HEAD) HEAD@{0}: pull: Fast-forward
7a8b80d (origin/cxxopts_migration) HEAD@{1}: pull: Fast-forward
414e6ee HEAD@{2}: clone: from https://github.com/trabucayre/openFPGALoader.git

The oldest commit does not support the Tang Nano, and neither of the newer ones work. Now that I think about it I'm not sure I ever used OpenFpgaLoader with Tang Nano or only with the Trenz GW1NR-9 board.

I'm trying to program my ColorLight-5a-75b with OpenFPGALoader, but I get the following output:

$ openFPGALoader -c usb-blaster -v blink.bit

found 1 devices
idcode 0x41111043
manufacturer lattice
model  LFE5U-25
family ECP5
File type : bit
Open file blink.bit DONE
Parse file DONE
Lattice bitstream header infos
Part: LFE5U-25F-6CABGA256
IDCode : 3000000
displayReadReg
	Config Target Selection : 0
	Overflow ERR
Enable configuration: FAIL
displayReadReg
	Config Target Selection : 0
	No err

I tried Googling around and it seems a similar bug has been fixed: bug

I can flash the FPGA with urjtag, using svf files.

I have an Arty S7-50 but the FPGA is not recognized by openFPGALoader from open-tool-forge. I do think the following diff should add the FPGA:

diff --git a/src/part.hpp b/src/part.hpp
index e81095a..c686ac9 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -16,6 +16,7 @@ static std::map <int, fpga_model> fpga_list = {
 
        {0x44008093, {"xilinx", "spartan6", "xc6slx45"}},
        {0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1"}},
+       {0x0362f093, {"xilinx", "spartan7", "xc7s50csga324-1"}},
 
        {0x020f30dd, {"altera", "cyclone 10 LP", "10CL025"}},
 

But due to #41 I can't test ATM.

I can't compile openFPGALoader on CentOS7, I get the following error:

[verhaegs@localhost build]$ LANG=en_US.utf8 make
[  4%] Building CXX object CMakeFiles/openFPGALoader.dir/src/ftdipp_mpsse.cpp.o
/home/verhaegs/eda/code/openFPGALoader/src/ftdipp_mpsse.cpp: In constructor ‘FTDIpp_MPSSE::FTDIpp_MPSSE(const FTDIpp_MPSSE::mpsse_bit_config&, const string&, uint32_t, bool)’:
/home/verhaegs/eda/code/openFPGALoader/src/ftdipp_mpsse.cpp:26:49: error: incompatible types in assignment of ‘const char [1]’ to ‘char [64]’
     _clkHZ(clkHZ), _buffer_size(2*32768), _num(0)
                                                 ^
/home/verhaegs/eda/code/openFPGALoader/src/ftdipp_mpsse.cpp: In constructor ‘FTDIpp_MPSSE::FTDIpp_MPSSE(const FTDIpp_MPSSE::mpsse_bit_config&, uint32_t, bool)’:
/home/verhaegs/eda/code/openFPGALoader/src/ftdipp_mpsse.cpp:52:51: error: incompatible types in assignment of ‘const char [1]’ to ‘char [64]’
       _clkHZ(clkHZ), _buffer_size(2*32768), _num(0)
                                                   ^
make[2]: *** [CMakeFiles/openFPGALoader.dir/src/ftdipp_mpsse.cpp.o] Error 1
make[1]: *** [CMakeFiles/openFPGALoader.dir/all] Error 2
make: *** [all] Error 2

I have following versions of libftdi and g++ installed:

[verhaegs@localhost build]$ rpm -q libftdi-devel gcc-c++
libftdi-devel-1.1-4.el7.x86_64
gcc-c++-4.8.5-39.el7.x86_64

Hi, I got a cyc1000 from Trenz attached to a raspberry pi 3 and tried your soft to send .svf files. After compiling and installing I can flash the test file sucesfully but at the end of the command the error "detach error -5" appears always. The test file seems to work but all my generated cores with quartus doesn´t work, looks like the flashing is correct but always get "end of flash" followed by the "detach error -5". Any clue of this?

Thanks.

Under Windows + MinGW, gowin_pack outputs a text fs file with CRLF end of lines.

It turns out ifstream::gcount() does not count two characters but only one for these, making the following file size check fail:

A simple external fix is to apply, e.g. dos2unix to convert the FS file end of lines.

Fixing this internally may require either reading in binary mode and making the parser compatible, or reading the file in a different way?

I recently tried to flash the ECP5 multiboot example in the ProjectTrellis Repo for the ECP5 evaluation board (LFE5UM5G-85F-EVN) but it failed during the "Refresh" step and the FPGA was not able to load the bitstream from th SPI flash (The Red LED D3 lit up and stayed on util I flashed a new program).
I used the following command:
openFPGALoader -c ft2232 -b ecp5_evn -f multiboot.mcs

Refresh: FAIL
displayReadReg
	Config Target Selection : 0
	SPIm Fail1
	Preamble ERR
	EXEC Error

I also tried flashing the blinky1.bit and blinky2.bit Bitstreams using the same command (to the onboard SPI Flash) which worked without problem.
I was also able to flash the multiboot.mcs file from ProjectTrellis with the official Lattice Diamond programmer util also without any problems.

I know that it's currently not supported, but is there any chance for it to be? The device is Bus 020 Device 010: ID 0547:1002 Anchor Chips Inc. USB-JTAG-Cable, but I guess the FPGA is the same (or at least similar) as on Lichee Tang nano?

That's a great tools. But not limited to Cyclone FPGA.
Why not changing the name ?

• fpgaloader, loadfpga
• configfpga, fpgaconf
• fpgaprog, progfpga
• ...

Is it possible to have less log messages when programming the FPGA ?

 $ ./cycloader -c digilent_hs3 pouet_impl1.jed
try to open 403 6014 -1 -1
found 1 devices
idcode 0x612bd043
funder lattice
model  MachXO3LF
family LCMX03LF-6900C
jed
G0
F0
fuse checksum C5343 AA 5343
inconnu
UH00000000
end
area[0] 0 269056
area[1] 269056 1172224
theorical checksum 5343 -> 5343
array size 2102
IDCode : 612bd043
00 08 0f 10 
displayReadReg
	Config Target Selection : 0
	JTAG Active
	Done Flag
	ISC Enable
	Write Enable
	Read Enable
	SDM Enable
	No err
flash erase
00 08 0e 10 
displayReadReg
	Config Target Selection : 0
	JTAG Active
	ISC Enable
	Write Enable
	Read Enable
	SDM Enable
	No err
00 08 0f 18 
displayReadReg
	Config Target Selection : 4
	JTAG Active
	Done Flag
	ISC Enable
	Write Enable
	Read Enable
	SDM Enable
	No err
flash erase
00 00 0e 18 
displayReadReg
	Config Target Selection : 4
	JTAG Active
	ISC Enable
	Write Enable
	Read Enable
	No err
Writing: [==================================================] 100.00%
Done
00 00 0e 18 
displayReadReg
	Config Target Selection : 4
	JTAG Active
	ISC Enable
	Write Enable
	Read Enable
	No err
Verifying: [==================================================] 100.00%
Done
00 00 0e 18 
displayReadReg
	Config Target Selection : 4
	JTAG Active
	ISC Enable
	Write Enable
	Read Enable
	No err
00 00 0e 18 
displayReadReg
	Config Target Selection : 4
	JTAG Active
	ISC Enable
	Write Enable
	Read Enable
	No err
00 00 00 00 00 00 00 00 
0600
	boot mode                                : Single Boot from NVCM/Flash
	Master Mode SPI                          : disable
	I2c port                                 : disable
	Slave SPI port                           : disable
	JTAG port                                : enable
	DONE                                     : disable
	INITN                                    : disable
	PROGRAMN                                 : enable
	My_ASSP                                  : disable
	Password (Flash Protect Key) Protect All : Disabled
	Password (Flash Protect Key) Protect     : Disabled
00 00 0e 18 
displayReadReg
	Config Target Selection : 4
	JTAG Active
	ISC Enable
	Write Enable
	Read Enable
	No err
00 08 0f 18 
displayReadReg
	Config Target Selection : 4
	JTAG Active
	Done Flag
	ISC Enable
	Write Enable
	Read Enable
	SDM Enable
	No err
00 08 01 00 
displayReadReg
	Config Target Selection : 0
	Done Flag
	SDM Enable
	No err
00 08 01 00 
displayReadReg
	Config Target Selection : 0
	Done Flag
	SDM Enable
	No err

Hi, I wanted to report that I have tested this software on a artix-7 200t device and so far it seems to work.
Using an FT2232 as download cable I only had to define the new part {0x13636093, {"xilinx", "artix a7 200t", "xc7a200"}}.

I only had some issues for the digilent nexys video board, where apparently the jtag is connected on the INTERFACE_B of the integrated FT2232 chip. So I just defined a new download cable {"digilentb", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_B, 0xe8, 0xeb, 0x00, 0x60}}}

Hi there!
I've been maintaining nightly builds of a selection of open fpga tools here https://github.com/open-tool-forge/fpga-toolchain Someone suggested adding openFPGALoader and it looks like it would be a great addition to the fpga-toolchain package.

I read #24 and if you are interested I'd like to help add Windows support so that I can provide nightly builds for Linux, OS X and Windows.

We're already building other tools using libusb/libftdi so those are no problem, but libargp is trickier. It looks like libargp has a standalone version for OS X but I couldn't find one for MinGW on Windows. I spent a little bit of time seeing what it would take to port to Windows and to be honest, it looks like it would be easier to use a different library. I was wondering if you would be open to a pull request using a different library to parse the command line arguments? Given that you are already set up to compile C++11 I think this single-header library would be a good fit https://github.com/jarro2783/cxxopts

If I run the program with option -v :

$ ./cycloader -c digilent_hs3 plop.jed -v
try to open 403 6014 -1 -1
found 1 devices
idcode 0x612bd043
funder lattice
model  MachXO3LF
family LCMX03LF-6900C
jed
G0
F0
fuse checksum C5343 AA 5343
inconnu
UH00000000
end
area[0] 0 269056
area[1] 269056 1172224
theorical checksum 5343 -> 5343
array size 2102
IDCode : 612bd043
Enable configuration: DONE
SRAM erase: DONE
Enable configuration: DONE
Flash erase: DONE
Writing: [==================================================] 100.000000%
Done
Verifying: [==================================================] 100.000000%
Done
Program features Row: DONE
Program feabitss: DONE
Write program Done: DONE
Disable configuration: DONE
Refresh: DONE

And without :

$ ./cycloader -c digilent_hs3 plop.jed
try to open 403 6014 -1 -1
found 1 devices
idcode 0x612bd043
funder lattice
model  MachXO3LF
family LCMX03LF-6900C
jed
G0
F0
fuse checksum C5343 AA 5343
inconnu
UH00000000
end
area[0] 0 269056
area[1] 269056 1172224
theorical checksum 5343 -> 5343
array size 2102
IDCode : 612bd043
Enable configuration: DONE
SRAM erase: DONE
Enable configuration: DONE
Flash erase: DONE
Writing: [==================================================] 100.000000%
Done
Verifying: [==================================================] 100.000000%
Done
Program features Row: DONE
Program feabitss: DONE
Write program Done: DONE
Disable configuration: DONE
Refresh: DONE

The Alchitry Au board is very similar to the Digilent Arty and Basys boards and should be easy to add support for.

can you add support for the Xilinx XC7A75T

now I use openFPGALoader -f -c digilent_hs3 ./Test.mcs have error:

Error: device 13632093 not supported

Thanks!

Color output is great, but sometimes we need no color (for logging, old terminal, ...).
It could be good to add nocolor option.

Would it be possible to add a --quiet option switch so that openFPGALoader does neither emit:

• = progression chars on stderr
• completion %-age on stdout
  This would be very useful to use it in unattended context (such as CI/CD), as it generates a large amount of text which makes the output harder to parse and not useful it this kind of context.

Thanks a lot for this tool, it seems to overcome many limitations encountered with xc3sprog, it is a pity it is much harder to find for now. I hope it will soon move up in search ranks!

I am unable to write to flash on my Lattice CrossLink-NX evaluation board. I have used this earlier on the Lattice ECP5 board - it works for me there.

Here is the what I see -- any idea what might be going wrong ?

$ ./build/openFPGALoader  -b crosslinknx_evn -f  /media/shkumar/Windows/Users/shkumar/my_designs/blinky/impl_1/blinky_impl_1.bit
write to flash
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Enable configuration: DONE
SRAM erase: DONE
Open file DONE
Parse file DONE
Detail: 
Jedec ID          : 00
memory type       : 00
memory capacity   : 00
Detail: 
Jedec ID          : 00
memory type       : 00
memory capacity   : 00
timeout: 0 0 1000
0
wait: Error
write en: Error
Erasing: [==================================================] 100.000000%
Fail
Refresh: DONE

Since 99929f9 I have had problems with using cables different from ftdi, as it throws the error "Error: FTDI serial param is for FTDI cables." Even without FTDI serial param specified.
Regards JD

Hi!
When i try to program TangNano, i see:
$ openFPGALoader -m -b tangnano led_prj/impl/pnr/led_prj.fs -v
found 1 devices
idcode 0x900281b
manufacturer Gowin
model GW1N-1
family GW1N
File type : fs
Parse led_prj/impl/pnr/led_prj.fs:
xBackgroundProgramming: OFF
xCRCCheck: ON
xCheckSum: 0xB0ED
xCompress: ON
xCreated Time: Tue Dec 15 11:31:02 2020
xDevice-package: GW1N-1-QFN48
xEncryption: OFF
xFile Title: Bitstream file
xGOWIN Version: V1.9.7Beta
xJTAGAsRegularIO: OFF
xLoadingRate: 2.667MHz
xPart Number: GW1N-LV1QN48C6/I5
xSPIAddr: 0x00fff000
xSecureMode: OFF
xSecurityBit: OFF
xUserCode: 0x0000B0ED
Segmentation fault (core dumped)

$ dmesg
[11730.387256] openFPGALoader[21674]: segfault at 55ab63abb000 ip 000055ab61c4edb3 sp 00007ffd46f43ad0 error 4 in openFPGALoader[55ab61ac3000+1d7000]
[11730.387262] Code: 00 00 83 bd f0 fe ff ff 0f 7f 61 8b 95 f0 fe ff ff 8b 85 ec fe ff ff 01 d0 89 c2 48 8d 45 80 48 89 d6 48 89 c7 e8 1d 8b f5 ff <0f> b6 00 3c 31 75 07 b8 01 00 00 00 eb 05 b8 00 00 00 00 66 89 85

I tried to flash the blinky demo on the Colorlight 5a-75b v7
any suggestions would be greatly appreciated.

First detect:

$ openFPGALoader -cft232 --detect
idcode 0x41111043
manufacturer lattice
model  LFE5U-25
family ECP5

then write bitstream to sram:

$ openFPGALoader -cft232 blink.bit 
Open file blink.bit DONE
Parse file DONE
Enable configuration: DONE
SRAM erase: DONE
Loading: [==================================================] 100.000000%
Fail
displayReadReg
	Config Target Selection : 0
	JTAG Active
	ISC Enable
	Write Enable
	Read Enable
	Std PreAmble
	SPIm Fail1
	SDM EOF
	EXEC Error
	Device failed to verify
	Invalid Command
	SED Error
	Bypass Mode
	FT Mode

$ openFPGALoader --board ulx3s --bitstream  ./build/ulx3s/gateware/top.bit -v
ret 0
found 1 devices
idcode 0x41113043
manufacturer lattice
model  LFE5U-85
family ECP5
File type : bit
Open file ./build/ulx3s/gateware/top.bit DONE
Parse file DONE
Lattice bitstream header infos
Part: LFE5U-45F-6CABGA381
IDCode : 41113043
displayReadReg
        Config Target Selection : 0
        Std PreAmble
        ID ERR
        EXEC Error
Enable configuration: DONE
SRAM erase: DONE
Loading: [==================================================] 100.000000%
Fail
displayReadReg
        Config Target Selection : 0
        JTAG Active
        ISC Enable
        Write Enable
        Read Enable
        Std PreAmble
        ID ERR
        EXEC Error

top.bit.zip

Programming a small "blinky" bitstream is successful though.

I'm too lazy to type openFPGALoader, is it possible to have a binary alias like ofl ?

$ ofl -?
Usage: ofl [OPTION...] BIT_FILE
openFPGALoader -- a program to flash FPGA

  -b, --board=BOARD          board name, may be used instead of cable
  -c, --cable=CABLE          jtag interface
  -d, --device=DEVICE        device to use (/dev/ttyUSBx)
  -o, --offset=OFFSET        start offset in EEPROM
  -r, --reset                reset FPGA after operations
  -v, --verbose              Produce verbose output
  -?, --help                 Give this help list
      --usage                Give a short usage message
  -V, --version              Print program version

Mandatory or optional arguments to long options are also mandatory or optional
for any corresponding short options.

Report bugs to <[email protected]>.

I'm using you tool (414e6ee) to program my Trenz Gowin board, and it actually works, but the tool reports failure. Not sure what is going on actually.

Parse pack.fs: Done
erase SRAM Done
Flash SRAM: [==================================================] 100.000000%
Done
SRAM Flash: FAIL

Hi
I have with success programed my tang nano with your tool, both:

openFPGALoader -m -b tangnano impl/pnr/*.fs

and

openFPGALoader -m -b littleBee impl/pnr/*.fs

Give a successful (volatile) flash
However (as stated) the -f option does not work (yet) and I would like to hear if you have plans for implementing the -f (flash) programming option any time soon for the GW1N-1 chip ?

Reason is that I cannot get the GOWIN linux version of the programmer to work on the tang nano (kde neon 18.04).

I have compiled and installed openFPGALoader (running into linker errors when compilig with -DBUILD_STATIC=ON or -DENABLE_UDEV=OFF, but just bypassing by leaving those flags out). Set up the udev rules, rebooted (multiple times) and tried

openFPGALoader -cdirtyJtag --detect

which results in

write to ram
getVersion: usb bulk write failed -7
Jtag frequency : requested 6000000Hz -> real 6000000Hz
setClkFreq: usb bulk write failed -7
Fail to set frequency
Error: Failed to claim cable

when unplugging dirtyjtag the following result occurs:

write to ram
fails to open device
Error: Failed to claim cable

after plug cycling:

write to ram
Jtag frequency : requested 6000000Hz -> real 6000000Hz
writeTDI: read: usb bulk read failed -7
writeTDI: fill: usb bulk write failed -7actual length: 0
writeTDI: fill: usb bulk write failed -7actual length: 0
writeTDI: fill: usb bulk write failed -7actual length: 0
writeTDI: fill: usb bulk write failed -7actual length: 0
sendBitBang: usb bulk write failed 1
sendBitBang: usb bulk write failed 1
sendBitBang: usb bulk write failed 1
sendBitBang: usb bulk write failed 1
sendBitBang: usb bulk write failed 1
sendBitBang: usb bulk write failed 1
Error: currently only one device is supported

the cable is detected correctly in urjtag and i can load FPGAs no problem...

I am running on Ubuntu 20.04 LTS

these are the installed packages:

-- Found PkgConfig: /usr/bin/pkg-config (found version "0.29.1") 
-- Checking for module 'libftdi1'
--   Found libftdi1, version 1.4
-- Checking for module 'libusb-1.0'
--   Found libusb-1.0, version 1.0.23
-- Checking for module 'libudev'
--   Found libudev, version 245

What am I doing wrong??
Regards

I have a need to program multiple MachXO2/3 parts on a single JTAG chain.

It doesn't look impossible to add this support...but I don't exactly have the time myself for this right now.

While testing the Altera USB blaster support in openFPGAloader, I decided to plug in my old Cyclone III EP3C25 based board.
To my surprise, it identified the chip as a Cyclone 10CL025.
While checking the openFPGAloader docs, I ran into this note:

Note: cyclone IV and cyclone 10 have same idcode. A WA is mandatory to detect correct model for flash programming.

Upon checking the Altera documentation, I saw that indeed EP4CE22, EP3C25 and apparently 10CL025, all share the same IDcode.
Checking the data sheet, all 3 chips have 594k bits of embedded memory, 66 multipliers, 4 PLLs, and 20 global clock networks.
Looking at the 3 families' Logic Element diagram reveals they are identical.

Could it be that all 3 devices share the same bitstream format, and the family difference is just a die shrink?
Actually, the Ep3C24 and the 10CL025 has the same number of LEs (24,624) but the EP4CE22 has slightly less LEs (22,320).

Also, does WA above stands for "Workaround"? Do you mean that while loading a bitstream may be identical, you can't program the flash withough knowing the exact device, because each device requires different bitstream file for programming flash devices that are connected to the FPGA?

Hi @trabucayre ,
Thank you for this software. I suggest you add a donation link to the readme for people who would like to support your work on this project.
You work has helped me avoid buying a rather costly programmer and I would like to thank you somehow.
Thanks

Looking to add support for the gowin gw2a-55 part.

I've added the following line to part.hpp:
{0x0000281B, {"Gowin", "GW2A", "GW2A-55"}},

I've tested on the DK-START-GW2A55-PG484 dev board and SRAM configuration programming works fine with this addition but the calculated checksum doesn't match the userCode checksum which causes it to report it failed. Any advice on how to reverse the checksum from the .fs file?

I'm trying to program the example design for the ULX3S (ECP5) from the nmigen-boards repository and openFPGALoader is crashing inconsistently. Sometimes it crashes; sometimes it doesn't. Sometimes the crashes are correlated with the design not running; sometimes the design runs just fine. Here's an example of what I see:

(.env) [vorash-debian:~/repro] python -m nmigen_boards.ulx3s 85F
ret 0
Open file /tmp/nmigen_e4eqy0e0_top.bit DONE
Parse file DONE
Enable configuration: DONE
SRAM erase: DONE
Loading: [===================                               ] 37.994545%problem -1 written
Loading: [=========================                         ] 48.850128%problem -1 written
Loading: [==================================================] 100.000000%
Done
Disable configuration: DONE
double free or corruption (out)
Traceback (most recent call last):
  File "/usr/lib/python3.8/runpy.py", line 194, in _run_module_as_main
    return _run_code(code, main_globals, None,
  File "/usr/lib/python3.8/runpy.py", line 87, in _run_code
    exec(code, run_globals)
  File "/home/sjo/repro/.env/lib/python3.8/site-packages/nmigen_boards/ulx3s.py", line 197, in <module>
    platform().build(Blinky(), do_program=True)
  File "/home/sjo/repro/.env/lib/python3.8/site-packages/nmigen/build/plat.py", line 103, in build
    self.toolchain_program(products, name, **(program_opts or {}))
  File "/home/sjo/repro/.env/lib/python3.8/site-packages/nmigen_boards/ulx3s.py", line 161, in toolchain_program
    subprocess.check_call([tool, "-b", "ulx3s", '-m', bitstream_filename])
  File "/usr/lib/python3.8/subprocess.py", line 364, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['openFPGALoader', '-b', 'ulx3s', '-m', '/tmp/nmigen_e4eqy0e0_top.bit']' died with <Signals.SIGABRT: 6>.

If I recompile openFPGALoader with -fsanitize-address, I consistently get output like the following:

(.env) [vorash-debian:~/repro] ~/fpga/tools/openFPGALoader-build/openFPGALoader -b ulx3s -m build/top.bit
ret 0
Open file build/top.bit DONE
Parse file DONE
Enable configuration: DONE
SRAM erase: DONE
Loading: [                                                  ] 0.000000%=================================================================
==25838==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x62100003d100 at pc 0x55910e641e01 bp 0x7fff3068a330 sp 0x7fff3068a328
WRITE of size 1 at 0x62100003d100 thread T0
    #0 0x55910e641e00 in FtdiJtagBitBang::writeTDI(unsigned char*, unsigned char*, unsigned int, bool) /home/sjo/fpga/tools/openFPGALoader/src/ftdiJtagBitbang.cpp:182
    #1 0x55910e637378 in Jtag::read_write(unsigned char*, unsigned char*, int, char) /home/sjo/fpga/tools/openFPGALoader/src/jtag.cpp:186
    #2 0x55910e6375c5 in Jtag::shiftDR(unsigned char*, unsigned char*, int, int) /home/sjo/fpga/tools/openFPGALoader/src/jtag.cpp:208
    #3 0x55910e747da1 in Lattice::program_mem() /home/sjo/fpga/tools/openFPGALoader/src/lattice.cpp:238
    #4 0x55910e74d30f in Lattice::program(unsigned int) /home/sjo/fpga/tools/openFPGALoader/src/lattice.cpp:526
    #5 0x55910e66b910 in main /home/sjo/fpga/tools/openFPGALoader/src/main.cpp:285
    #6 0x7f97697dacc9 in __libc_start_main ../csu/libc-start.c:308
    #7 0x55910e5d5029 in _start (/home/sjo/fpga/tools/openFPGALoader-build/openFPGALoader+0x113029)

0x62100003d100 is located 0 bytes to the right of 4096-byte region [0x62100003c100,0x62100003d100)
allocated by thread T0 here:
    #0 0x7f9769c601f8 in __interceptor_realloc (/lib/x86_64-linux-gnu/libasan.so.6+0xaa1f8)
    #1 0x55910e641034 in FtdiJtagBitBang::FtdiJtagBitBang(FTDIpp_MPSSE::mpsse_bit_config const&, jtag_pins_conf_t const*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, unsigned int, bool) /home/sjo/fpga/tools/openFPGALoader/src/ftdiJtagBitbang.cpp:73
    #2 0x55910e6363e6 in Jtag::init_internal(cable_t&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, jtag_pins_conf_t const*, unsigned int) /home/sjo/fpga/tools/openFPGALoader/src/jtag.cpp:95
    #3 0x55910e635ffb in Jtag::Jtag(cable_t&, jtag_pins_conf_t const*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, unsigned int, bool) /home/sjo/fpga/tools/openFPGALoader/src/jtag.cpp:76
    #4 0x55910e66a8b3 in main /home/sjo/fpga/tools/openFPGALoader/src/main.cpp:219
    #5 0x7f97697dacc9 in __libc_start_main ../csu/libc-start.c:308

SUMMARY: AddressSanitizer: heap-buffer-overflow /home/sjo/fpga/tools/openFPGALoader/src/ftdiJtagBitbang.cpp:182 in FtdiJtagBitBang::writeTDI(unsigned char*, unsigned char*, unsigned int, bool)
Shadow bytes around the buggy address:
  0x0c427ffff9d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c427ffff9e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c427ffff9f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c427ffffa00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c427ffffa10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
=>0x0c427ffffa20:[fa]fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
  0x0c427ffffa30: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
  0x0c427ffffa40: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
  0x0c427ffffa50: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
  0x0c427ffffa60: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
  0x0c427ffffa70: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
Shadow byte legend (one shadow byte represents 8 application bytes):
  Addressable:           00
  Partially addressable: 01 02 03 04 05 06 07 
  Heap left redzone:       fa
  Freed heap region:       fd
  Stack left redzone:      f1
  Stack mid redzone:       f2
  Stack right redzone:     f3
  Stack after return:      f5
  Stack use after scope:   f8
  Global redzone:          f9
  Global init order:       f6
  Poisoned by user:        f7
  Container overflow:      fc
  Array cookie:            ac
  Intra object redzone:    bb
  ASan internal:           fe
  Left alloca redzone:     ca
  Right alloca redzone:    cb
  Shadow gap:              cc
==25838==ABORTING

For reference, here are the software versions I used to produce the above outputs:

• nmigen-boards: 0.1.dev168+gb90a89d
• nmigen: 0.3.dev228+g59ef6e6
• yosys: 0.9+3696 (git sha1 45725d3b, clang 9.0.1-15+b1 -fPIC -Os)
• ecppack (prjtrellis): 1.0-476-ga441cd9
• nextpnr-ecp5: 89552307
• openFPGALoader: 5b19775

And here's what I used to build openFPGALoader itself (all from Debian):

• gcc: Debian 10.2.0-16
• libusb-1.0: 2:1.0.23-2
• libftdi1-2: 1.5-5
• libudev1: 246.6-4

I also tried backing up to openFPGALoader v0.1, which fails in a similar way but with a different error message:

(.env) [vorash-debian:~/repro] ~/fpga/tools/openFPGALoader-build/openFPGALoader -b ulx3s -m build/top.bit
ret 0
Open file build/top.bit DONE
Parse file DONE
Enable configuration: DONE
SRAM erase: DONE
Loading: [=======================                           ] 44.146042%problem -1 written
Loading: [======================================            ] 75.989090%problem -1 written
malloc(): invalid size (unsorted)
zsh: abort      ~/fpga/tools/openFPGALoader-build/openFPGALoader -b ulx3s -m build/top.bit

Hello,
today I observed a possible hang that might occur when the FT2232H is left in a certain state by another software. The problem can be reproduce with the following:

1. program a fpga using the interface B of the FT2232H
2. run another software that uses the interface A of the FT2232H in BITMODE_SYNCFF mode.
3. trying to reprogram the FPGA again, openFPGAloader hang even before the progress bar appears.

Turns out the other software wasn't resetting the interface A by setting BITMODE_RESET before exiting;
As described in the manual, the FT2232H, and possibly other similar multichannel devices, can lose access to one interface when programmed in certain modes such as SYNCFF.

This is probably a very specific corner case, but I find surprising that libftdi doesn't generate any error when opening, configuring and writing/reading an interface that is not usable in that particular configuration. Anyway I think it might be good idea to extend the reset procedure in openFPGALoader, by setting BITMODE_SYNCFF on all interfaces on initialization.

VBUS must be connected to pin 5 of U4 (ESDU5V0H4 near USB connector), not +3V3. Schematic V3.

Hi
Would it be possible to add "MachXO2" to the supported devices?
I would like to program "lcmxo2-7000hc-4ftg256c"
http://www.latticesemi.com/view_document?document_id=38834
is it possible? Thank you

openFPGA loader looks promising, but I see it is targeted to Linux with glibc only. Do you have any plans to port it to something else?

Current problems I see are:

• dependency on udev without ifdefs and cmake option
• dependency on argp which is glibc specific (musl libc does not have it by default, also other OSes than Linux)

Is there an option to list supported cables ?
Same question for board.

HI

I'd like if there is some option to flash given file unmodified,
directly to flash chip, starting from some offset.

To make code simpler, It's acceptable if offset
has to be multiple of 4K or 64K what I think is erase
block size.

HI!

I suggest gzip on-the-fly decompression to upload bitstreams.
Especially it's good for spi-over-jtag bitstreams database
each one from 2MB becomes only 3.3KB with gzip -9

Hi!,

I am using an JTAG-USB with FTDI FT2232D chip inside.

Typing:

$ lsusb

result in:

...
Bus 003 Device 011: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
...

So it is recognized. However, when I set the command:

$ openFPGALoader -f -b licheeTang /home/nacho/FPGA/Tang_FPGA_Examples/2.LCD/test_lcd.bit

results in:

fails to open device
Error: Failed to claim cable

Any hints on what could the problem be?

Thanks in advance.