trinhgiahuy Goto Github PK

followers: 45.0 following: 444.0 repos: 247.0 gists: 8.0

Type: User

Company: Tuni

Bio: Embedded Stack Enthusiasm Medium: https://medium.com/@trnhgiahuy_42112

Location: Tampere, Finland

Blog: https://github.com/giahuytrinh

🔭 I’m currently working on https://gitlab.com/giahuy050201/a64fxCvC
👯 I’m looking to collaborate on Sparse Computing/CGRA Topics

Languages and Tools:

Current and Future learn:

OTHER REFERENCE

Pass for Ubuntu 18 WSL2:

username: huy, passw: huy

Some good sources I found

Convert a 5V Arduino Nano clone to run on 3.3V

Lean2 Embedded systems without the bloat

https://inst.eecs.berkeley.edu/~cs150/sp13/agenda/lec/

http://web.mit.edu/6.111/www/f2017/handouts/

https://github.com/sakarivelho

Bash Script Tutorial

Bash: Get the Exit Status Code of the Last Command

Bash-Ubuntu-AWS tutorial

EmbeTronicX

iotforall

Learn BeagleBone Black Embedded

GOOD AUTHOR FOR SE

Steve Jansen

ML INFERECNCE ON PICO PROJECT:

Same tut

ML Nano BLE 33 & RPi

TinyML - Motion Recognition Using Pico

ArduCAM

Person Detection on Raspberry Pi Pico with ArduCAM and TensorFlow Lite

Using ADXL-335

TinyML Implementation using Raspberry Pi Pico: Geometry Gesture Detection (Part-II)

trinhgiahuy's Projects

cluster-resource-benchmarking

Evaluating Benchmarking of Compute resources such as CPU, Disk, Memory and Network

coding-interview-university

A complete computer science study plan to become a software engineer.

combinational_lock_fpga_verilog

FPGA-based lock for 8-digit number. Lock works in the same way as bicycle lock, it is 8-digit password. Program has user interface: 8-digit LED display, indicators for state of the program. FPGA model: ALTERA Cyclone IV EP4CE6E22C8N. Programming language: Verilog HDL. IDE: Quartus Prime Light Edition. Project authors: Shevchenko Makar Ilyich, Murashko Artem Maximovich, Chernitsa Artem Alexandrovich. Thanks to: Burmyakov Artem, Tormasov Alexander, Ostankovich Vladislav, Muhammad Fahim, Voronov Artem, Innopolis University.