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RISC-V CPU Core (RV32IM)

License: BSD 3-Clause "New" or "Revised" License

Verilog 68.48% Makefile 0.55% C++ 27.63% C 3.34%

risc-v cpu verilog fpga verilator rv32im rv32i riscv-linux pipeline-processor asic

riscv's Introduction

RISC-V Core

Github: http://github.com/ultraembedded/riscv

A 32-bit RISC-V core written in Verilog and an instruction set simulator supporting RV32IM.
This core has been tested against a co-simulation model and exercised on FPGA.

For a higher performance dual issue CPU with branch prediction, see my latest RISC-V core here; http://github.com/ultraembedded/biriscv

Overview

Features

32-bit RISC-V ISA CPU core.
Support RISC-V integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).
Supports user, supervisor and machine mode privilege levels.
Basic MMU support - capable of booting Linux with atomics (RV-A) SW emulation.
Implements base ISA spec v2.1 and privileged ISA spec v1.11.
Verified using Google's RISCV-DV random instruction sequences using cosimulation against C++ ISA model.
Support for instruction / data cache, AXI bus interfaces or tightly coupled memories.
Configurable number of pipeline stages and result forwarding options.
Synthesizable Verilog 2001, Verilator and FPGA friendly.
Coremark: 2.94 CoreMark/MHz
Dhrystone: 1.25 DMIPS/MHz ('legal compile options' / 337 instructions per iteration)
Want higher performance (4.1CM/MHz / 1.9DMIPS/MHz) - see my improved core.

Configuration

Param Name	Valid Range	Description
SUPPORT_SUPER	1/0	Enable supervisor / user privilege levels.
SUPPORT_MMU	1/0	Enable basic memory management unit.
SUPPORT_MULDIV	1/0	Enable HW multiply / divide (RV-M).
SUPPORT_LOAD_BYPASS	1/0	Support load result bypass paths.
SUPPORT_MUL_BYPASS	1/0	Support multiply result bypass paths.
SUPPORT_REGFILE_XILINX	1/0	Support Xilinx optimised register file.
EXTRA_DECODE_STAGE	1/0	Extra decode pipe stage for improved timing.
MEM_CACHE_ADDR_MIN	32'h0 - 32'hffffffff	Lowest cacheable memory address.
MEM_CACHE_ADDR_MAX	32'h0 - 32'hffffffff	Highest cacheable memory address.

Directories

Name	Contents
core/riscv	RISC-V pipelined RV32IM CPU core (Verilog)
isa_sim	Instruction set simulator (C)
top_tcm_axi/src_v	Example instance with 64KB DP-RAM & AXI Interfaces
top_tcm_axi/tb	System-C testbench for the core
top_cache_axi/src_v	Example instance with instruction and data caches.
top_cache_axi/tb	System-C testbench for the core

Example Core Instance (with TCM memory)

The top (top_tcm_axi/src_v/riscv_tcm_top.v) contains;

Instances one of the above cores, adding RAM and standard bus interfaces.
64KB dual ported RAM for (I/D code and data).
AXI4 slave port for loading the RAM, DMA access, etc (including support for burst access).
AXI4-Lite master port for CPU access to peripherals.
Separate reset for CPU core to dual ported RAM / AXI interface (to allow program code to be loaded prior to CPU reset de-assertion).

Memory Map

Range	Description
0x0000_0000 - 0x0000_ffff	64KB TCM Memory
0x0000_2000	Boot address (configurable, see RISCV_BOOT_ADDRESS)
0x8000_0000 - 0xffff_ffff	Peripheral address space (from AXI4-L port)

Interfaces

Name	Description
clk_i	Clock input
rst_i	Async reset, active-high. Reset memory / AXI interface.
rst_cpu_i	Async reset, active-high. Reset CPU core (excluding AXI / memory).
axi_t_*	AXI4 slave interface for access to 64KB TCM memory.
axi_i_*	AXI4-Lite master interface for CPU access to peripherals.
intr_i	Active high interrupt input (for connection external int controller).

Testbench

A basic System-C / Verilator based testbench for the core is provided.

Dependencies;

gcc
make
libelf
System-C (specify path using SYSTEMC_HOME)
Verilator (specify path using VERILATOR_SRC)

To build the testbench;

cd top_tcm_axi/tb
make

To run the provided test executable;

cd top_tcm_axi/tb
make run

Example Core Instance (with caches)

The top (top_cache_axi/src_v/riscv_top.v) contains;

Instances one of the above cores, adding RAM and standard bus interfaces.
16KB 2-way set associative instruction cache
16KB 2-way set associative data cache with write-back and allocate on write.
2 x AXI4 master port for CPU access to instruction / data / peripherals.

Interfaces

Name	Description
clk_i	Clock input
rst_i	Async reset, active-high. Reset memory / AXI interface.
axi_i_*	AXI4 master interface for CPU access to instruction memory.
axi_d_*	AXI4 master interface for CPU access to data / peripheral memories.
intr_i	Active high interrupt input (for connection external int controller).
reset_vector_i	Boot vector.

Execution Example

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riscv's Issues

Need $SYSTEMC_INCLUDE in environment or when Verilator configured, and need $SYSTEMC_LIBDIR in environment or when Verilator configured Probably System-C isn't installed, see http://www.systemc.org

I have systemc installed in my machine but this problem still exists

Link error

Hi,
I tried this nice project in a unix environment.
It compiles but I had to use additional compilation flags:
-std=c++11
-D_GLIBCXX_USE_CXX11_ABI=0

Now the link error:
g++ -O2 -L*** -L./lib -L../../isa_sim obj/riscv_tcm_top_rtl.o obj/main.o -o build/test.x -lsystemc -lisa_sim -lsyscverilated -lelf -lbfd
obj/main.o: In function testbench::process()': main.cpp:(.text._ZN9testbench7processEv[_ZN9testbench7processEv]+0x41): undefined reference to cosim::attach_cpu(std::string, cosim_cpu_api*)'
main.cpp:(.text._ZN9testbench7processEv[_ZN9testbench7processEv]+0x8a): undefined reference to cosim::attach_mem(std::string, cosim_mem_api*, unsigned int, unsigned int)' ld: build/test.x: hidden symbol bfd_check_format_matches' in /usr/lib64/libbfd.a(format.o) is referenced by DSO
ld: final link failed: Bad value

Looking inside the content of isa_sim library, it seems to be there though:
0000000000009e60 T cosim::attach_cpu(std::__cxx11::basic_string<char, std::char_traits, std::allocator >, cosim_cpu_api*)
0000000000009f30 T cosim::attach_mem(std::__cxx11::basic_string<char, std::char_traits, std::allocator >, cosim_mem_api*, unsigned int, unsigned int)

The Problem of the method to generate basic.elf

Hello, I am trying to run helloworld.c on your RISC-V Core. Howevr It can't execute helloworld.c normally on it.
First ,I have already turn the C code into elf file and put it in the folder riscv/isa_sim/images.
Then, I call "make" in the folder riscv/isa_sim.
Finally, I type "./riscv-sim -f images/hello.elf" in the folder riscv/isa_sim.
Unfortunately, It fail due to the bad memory access.

So I am considering how is your basic.elf been generate ?
And what is the original basic.c ?

Thank you ~！！

A probable BUG at fetch stage.

For version 5ce4718.
The module "riscv_fetch" in RV32I core reads instruction from ICache, it feds "fetch_instr_o" and "fetch_pc_o" to "riscv_decode" module. The "fetch_pc_o" is registered for one clock cycle, but "fetch_instr_o" is not. Thus, the pc and instruction seen by the decoder do not match.

This probably won't cause errors when the core executes algorithm and memory instruction. But after executing branch instruction like "JALR", the first instruction of the branched address is ignored by the core, which causes core function error.

Output data is always zero

Hi, when I try to stimulate using the RISCV instruction set according to the manual, the output data is always zero. Can i have your help?

Quartus II

Is it possible to run this code in quartus II?

basic.elf source code

Please, can you provide the sources files of basic.elf?

Failed to operate top_tcm_axi

---------------------- My setup -------------------------
OS: Ubuntu 18.04
gcc / g++: 7.5.0
verilator: 4.111 devel rev v4.110-1-gdfd54a6a
systemc-2.3.3

When I tried to "make" in /riscv/top_tcm_axi/tb, I met the error logs.

I wonder what occurs the errors about VL_ATTR_COLD and how to I could solve it.

Could I get some help?

--------------------- Error Logs ----------------------------

axi4.h axi4_lite.h main.cpp makefile makefile.build_sysc_tb makefile.build_verilated makefile.generate_verilated obj_verilated riscv_tcm_top_rtl.cpp riscv_tcm_top_rtl.h sc_reset_gen.h testbench.h testbench_vbase.h verilated
bjkim@GPU2:~/riscv/top_tcm_axi/tb$ make
make -C ../../isa_sim lib
make[1]: Entering directory '/home/bjkim/riscv/isa_sim'
g++ -shared -o libisa_sim.a obj/riscv-sim/riscv.o obj/riscv-sim/riscv_inst_dump.o obj/riscv-sim/cosim_api.o obj/riscv-sim/riscv_main.o obj/riscv-sim/elf_load.o obj/riscv-sim/main.o
make[1]: Leaving directory '/home/bjkim/riscv/isa_sim'
make -f makefile.generate_verilated CORE=riscv
make[1]: Entering directory '/home/bjkim/riscv/top_tcm_axi/tb'
verilator --sc ../src_v/riscv_tcm_top --Mdir verilated -I./../src_v -I../../core/riscv --pins-sc-uint --l2-name v --trace
make[1]: Leaving directory '/home/bjkim/riscv/top_tcm_axi/tb'
make -f makefile.build_verilated
make[1]: Entering directory '/home/bjkim/riscv/top_tcm_axi/tb'
g++ -DVM_TRACE=1 -DVL_USER_FINISH=1 -fpic -Iverilated/ -I/home/bjkim/sysc/include -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -c verilated//Vriscv_tcm_top__Syms.cpp -o obj_verilated/Vriscv_tcm_top__Syms.o
In file included from verilated//Vriscv_tcm_top__Syms.h:15:0,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top.h:158:26: error: expected ‘;’ at end of member declaration
void _ctor_var_reset() VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top.h:158:28: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
void _ctor_var_reset() VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top.h:166:71: error: expected ‘;’ at end of member declaration
static void _eval_initial(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top.h:166:73: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _eval_initial(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top.h:167:70: error: expected ‘;’ at end of member declaration
static void _eval_settle(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top.h:167:72: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _eval_settle(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top.h:169:73: error: expected ‘;’ at end of member declaration
static void _settle__TOP__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top.h:169:75: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top.h:170:73: error: expected ‘;’ at end of member declaration
static void _settle__TOP__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top.h:170:75: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top.h:175:64: error: expected ‘;’ at end of member declaration
static void traceFullSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top.h:175:66: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceFullSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top.h:176:64: error: expected ‘;’ at end of member declaration
static void traceFullTop0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top.h:176:66: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceFullTop0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top.h:177:64: error: expected ‘;’ at end of member declaration
static void traceInitSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top.h:177:66: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceInitSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top.h:178:63: error: expected ‘;’ at end of member declaration
static void traceInitTop(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top.h:178:65: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceInitTop(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top.h:179:44: error: expected ‘;’ at end of member declaration
void traceRegister(VerilatedVcd* tracep) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top.h:179:46: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
void traceRegister(VerilatedVcd* tracep) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top.h:180:75: error: expected ‘;’ at end of member declaration
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top.h:180:77: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
In file included from /usr/share/verilator/include/verilated_sc.h:30:0,
from verilated//Vriscv_tcm_top__Syms.h:11,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top.h:181:19: error: ‘VL_CACHE_LINE_BYTES’ was not declared in this scope
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
^
/usr/share/verilator/include/verilatedos.h:37:62: note: in definition of macro ‘VL_ATTR_ALIGNED’

define VL_ATTR_ALIGNED(alignment) attribute ((aligned (alignment)))

                                                          ^~~~~~~~~

In file included from verilated//Vriscv_tcm_top__Syms.h:16:0,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_tcm_top.h:139:26: error: expected ‘;’ at end of member declaration
void _ctor_var_reset() VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_tcm_top.h:139:28: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
void _ctor_var_reset() VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_tcm_top.h:143:76: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_tcm_top.h:143:78: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_tcm_top.h:144:76: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_tcm_top.h:144:78: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_tcm_top.h:146:75: error: expected ‘;’ at end of member declaration
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_tcm_top.h:146:77: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
In file included from /usr/share/verilator/include/verilated_sc.h:30:0,
from verilated//Vriscv_tcm_top__Syms.h:11,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_tcm_top.h:147:19: error: ‘VL_CACHE_LINE_BYTES’ was not declared in this scope
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
^
/usr/share/verilator/include/verilatedos.h:37:62: note: in definition of macro ‘VL_ATTR_ALIGNED’

define VL_ATTR_ALIGNED(alignment) attribute ((aligned (alignment)))

                                                          ^~~~~~~~~

In file included from verilated//Vriscv_tcm_top__Syms.h:17:0,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_core__M0_MBffffffff.h:231:26: error: expected ‘;’ at end of member declaration
void _ctor_var_reset() VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_core__M0_MBffffffff.h:231:28: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
void _ctor_var_reset() VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_core__M0_MBffffffff.h:239:84: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__u_core__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_core__M0_MBffffffff.h:239:86: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__u_core__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_core__M0_MBffffffff.h:240:84: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__u_core__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_core__M0_MBffffffff.h:240:86: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__u_core__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_core__M0_MBffffffff.h:241:84: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__u_core__3(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_core__M0_MBffffffff.h:241:86: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__u_core__3(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_core__M0_MBffffffff.h:243:75: error: expected ‘;’ at end of member declaration
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_core__M0_MBffffffff.h:243:77: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
In file included from /usr/share/verilator/include/verilated_sc.h:30:0,
from verilated//Vriscv_tcm_top__Syms.h:11,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_core__M0_MBffffffff.h:244:19: error: ‘VL_CACHE_LINE_BYTES’ was not declared in this scope
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
^
/usr/share/verilator/include/verilatedos.h:37:62: note: in definition of macro ‘VL_ATTR_ALIGNED’

define VL_ATTR_ALIGNED(alignment) attribute ((aligned (alignment)))

                                                          ^~~~~~~~~

In file included from verilated//Vriscv_tcm_top__Syms.h:18:0,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_tcm_mem.h:134:26: error: expected ‘;’ at end of member declaration
void _ctor_var_reset() VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_tcm_mem.h:134:28: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
void _ctor_var_reset() VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_tcm_mem.h:138:83: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__u_tcm__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_tcm_mem.h:138:85: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__u_tcm__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_tcm_mem.h:142:75: error: expected ‘;’ at end of member declaration
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_tcm_mem.h:142:77: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
In file included from /usr/share/verilator/include/verilated_sc.h:30:0,
from verilated//Vriscv_tcm_top__Syms.h:11,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_tcm_mem.h:143:19: error: ‘VL_CACHE_LINE_BYTES’ was not declared in this scope
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
^
/usr/share/verilator/include/verilatedos.h:37:62: note: in definition of macro ‘VL_ATTR_ALIGNED’

define VL_ATTR_ALIGNED(alignment) attribute ((aligned (alignment)))

                                                          ^~~~~~~~~

In file included from verilated//Vriscv_tcm_top__Syms.h:19:0,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_csr__SB0.h:106:26: error: expected ‘;’ at end of member declaration
void _ctor_var_reset() VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_csr__SB0.h:106:28: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
void _ctor_var_reset() VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_csr__SB0.h:112:91: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__u_core__u_csr__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_csr__SB0.h:112:93: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__u_core__u_csr__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_csr__SB0.h:113:91: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__u_core__u_csr__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_csr__SB0.h:113:93: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__u_core__u_csr__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_csr__SB0.h:114:91: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__u_core__u_csr__3(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_csr__SB0.h:114:93: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__u_core__u_csr__3(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_csr__SB0.h:116:75: error: expected ‘;’ at end of member declaration
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_csr__SB0.h:116:77: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
In file included from /usr/share/verilator/include/verilated_sc.h:30:0,
from verilated//Vriscv_tcm_top__Syms.h:11,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_csr__SB0.h:117:19: error: ‘VL_CACHE_LINE_BYTES’ was not declared in this scope
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
^
/usr/share/verilator/include/verilatedos.h:37:62: note: in definition of macro ‘VL_ATTR_ALIGNED’

define VL_ATTR_ALIGNED(alignment) attribute ((aligned (alignment)))

                                                          ^~~~~~~~~

In file included from verilated//Vriscv_tcm_top__Syms.h:20:0,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_issue.h:236:26: error: expected ‘;’ at end of member declaration
void _ctor_var_reset() VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_issue.h:236:28: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
void _ctor_var_reset() VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_issue.h:242:93: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__u_core__u_issue__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_issue.h:242:95: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__u_core__u_issue__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_issue.h:243:93: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__u_core__u_issue__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_issue.h:243:95: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__u_core__u_issue__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_issue.h:256:75: error: expected ‘;’ at end of member declaration
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_issue.h:256:77: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
In file included from /usr/share/verilator/include/verilated_sc.h:30:0,
from verilated//Vriscv_tcm_top__Syms.h:11,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_issue.h:257:19: error: ‘VL_CACHE_LINE_BYTES’ was not declared in this scope
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
^
/usr/share/verilator/include/verilatedos.h:37:62: note: in definition of macro ‘VL_ATTR_ALIGNED’

define VL_ATTR_ALIGNED(alignment) attribute ((aligned (alignment)))

                                                          ^~~~~~~~~

In file included from verilated//Vriscv_tcm_top__Syms.h:21:0,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_tcm_mem_ram.h:58:26: error: expected ‘;’ at end of member declaration
void _ctor_var_reset() VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_tcm_mem_ram.h:58:28: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
void _ctor_var_reset() VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_tcm_mem_ram.h:62:75: error: expected ‘;’ at end of member declaration
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_tcm_mem_ram.h:62:77: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
In file included from /usr/share/verilator/include/verilated_sc.h:30:0,
from verilated//Vriscv_tcm_top__Syms.h:11,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_tcm_mem_ram.h:63:19: error: ‘VL_CACHE_LINE_BYTES’ was not declared in this scope
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
^
/usr/share/verilator/include/verilatedos.h:37:62: note: in definition of macro ‘VL_ATTR_ALIGNED’

define VL_ATTR_ALIGNED(alignment) attribute ((aligned (alignment)))

                                                          ^~~~~~~~~

In file included from verilated//Vriscv_tcm_top__Syms.h:22:0,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_csr_regfile.h:117:26: error: expected ‘;’ at end of member declaration
void _ctor_var_reset() VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_csr_regfile.h:117:28: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
void _ctor_var_reset() VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_csr_regfile.h:123:102: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__u_core__u_csr__u_csrfile__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_csr_regfile.h:123:104: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__u_core__u_csr__u_csrfile__1(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_csr_regfile.h:124:102: error: expected ‘;’ at end of member declaration
static void _settle__TOP__v__u_core__u_csr__u_csrfile__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_csr_regfile.h:124:104: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void _settle__TOP__v__u_core__u_csr__u_csrfile__2(Vriscv_tcm_top__Syms* __restrict vlSymsp) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_csr_regfile.h:127:75: error: expected ‘;’ at end of member declaration
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_csr_regfile.h:127:77: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
In file included from /usr/share/verilator/include/verilated_sc.h:30:0,
from verilated//Vriscv_tcm_top__Syms.h:11,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_csr_regfile.h:128:19: error: ‘VL_CACHE_LINE_BYTES’ was not declared in this scope
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
^
/usr/share/verilator/include/verilatedos.h:37:62: note: in definition of macro ‘VL_ATTR_ALIGNED’

define VL_ATTR_ALIGNED(alignment) attribute ((aligned (alignment)))

                                                          ^~~~~~~~~

In file included from verilated//Vriscv_tcm_top__Syms.h:23:0,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_regfile.h:86:26: error: expected ‘;’ at end of member declaration
void _ctor_var_reset() VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_regfile.h:86:28: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
void _ctor_var_reset() VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
verilated//Vriscv_tcm_top_riscv_regfile.h:91:75: error: expected ‘;’ at end of member declaration
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^
verilated//Vriscv_tcm_top_riscv_regfile.h:91:77: error: ‘VL_ATTR_COLD’ does not name a type; did you mean ‘VL_ATTR_PURE’?
static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
^~~~~~~~~~~~
VL_ATTR_PURE
In file included from /usr/share/verilator/include/verilated_sc.h:30:0,
from verilated//Vriscv_tcm_top__Syms.h:11,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
verilated//Vriscv_tcm_top_riscv_regfile.h:92:19: error: ‘VL_CACHE_LINE_BYTES’ was not declared in this scope
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
^
/usr/share/verilator/include/verilatedos.h:37:62: note: in definition of macro ‘VL_ATTR_ALIGNED’

define VL_ATTR_ALIGNED(alignment) attribute ((aligned (alignment)))

                                                          ^~~~~~~~~

verilated//Vriscv_tcm_top__Syms.h:58:19: error: ‘VL_CACHE_LINE_BYTES’ was not declared in this scope
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
^
/usr/share/verilator/include/verilatedos.h:37:62: note: in definition of macro ‘VL_ATTR_ALIGNED’

define VL_ATTR_ALIGNED(alignment) attribute ((aligned (alignment)))

                                                          ^~~~~~~~~

verilated//Vriscv_tcm_top__Syms.cpp: In constructor ‘Vriscv_tcm_top__Syms::Vriscv_tcm_top__Syms(Vriscv_tcm_top*, const char*)’:
verilated//Vriscv_tcm_top__Syms.cpp:60:99: error: ‘SCOPE_OTHER’ is not a member of ‘VerilatedScope’
__Vscope_v__u_tcm__u_ram.configure(this, name(), "v.u_tcm.u_ram", "u_ram", 0, VerilatedScope::SCOPE_OTHER);
^~~~~~~~~~~
verilated//Vriscv_tcm_top__Syms.cpp:63:147: error: no matching function for call to ‘VerilatedScope::varInsert(int&, const char [4], IData ()[16384], bool, VerilatedVarType, int, int, int, int, int, int)’
__Vscope_v__u_tcm__u_ram.varInsert(__Vfinal,"ram", &(TOP__v__u_tcm__u_ram.ram), false, VLVT_UINT32,VLVD_NODIR|VLVF_PUB_RW,2 ,31,0 ,16383,0);
^
In file included from /usr/share/verilator/include/verilated_heavy.h:32:0,
from verilated//Vriscv_tcm_top__Syms.h:12,
from verilated//Vriscv_tcm_top__Syms.cpp:4:
/usr/share/verilator/include/verilated.h:285:10: note: candidate: void VerilatedScope::varInsert(int, const char, void*, VerilatedVarType, int, int, ...)
void varInsert(int finalize, const char* namep, void* datap,
^~~~~~~~~
/usr/share/verilator/include/verilated.h:285:10: note: no known conversion for argument 4 from ‘bool’ to ‘VerilatedVarType’
makefile.build_verilated:52: recipe for target 'obj_verilated/Vriscv_tcm_top__Syms.o' failed
make[1]: *** [obj_verilated/Vriscv_tcm_top__Syms.o] Error 1
make[1]: Leaving directory '/home/bjkim/riscv/top_tcm_axi/tb'
makefile:21: recipe for target 'build' failed
make: *** [build] Error 2

compile erros

Hi,I got the code and compile,but get errors as flow:

g++ -fpic -O2 -I./ -I./verilated -I../../isa_sim -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I/usr/local/systemc_2.3.3/include -DVM_TRACE=1 -c main.cpp -o obj/main.o
In file included from main.cpp:2:0:
testbench.h: In member function ‘virtual void testbench::write(uint32_t, uint8_t)’:
testbench.h:109:23: error: ‘struct Vriscv_tcm_top’ has no member named ‘v’
m_dut->m_rtl->v->u_mem_tcm->write(addr, data);
^
testbench.h: In member function ‘virtual uint8_t testbench::read(uint32_t)’:
testbench.h:116:30: error: ‘struct Vriscv_tcm_top’ has no member named ‘v’
return m_dut->m_rtl->v->u_mem_tcm->read(addr);
^

Run $make under top_tcm_axi/tb/

hello, I try to run the makefile under top_tcm_axi/tb, but got some error as follow:

In file included from main.cpp:2:
testbench.h: In member function ‘virtual void testbench::write(uint32_t, uint8_t)’:
testbench.h:111:23: error: ‘struct Vriscv_tcm_top’ has no member named ‘__VlSymsp’; did you mean ‘Vriscv_tcm_top__Syms* const Vriscv_tcm_top::vlSymsp’? (not accessible from this context)
111 | m_dut->m_rtl->__VlSymsp->TOP__v__u_tcm.write(addr, data);
| ^~~~~~~~~
In file included from testbench.h:12,
from main.cpp:2:
./verilated/Vriscv_tcm_top.h:26:33: note: declared private here
26 | Vriscv_tcm_top__Syms* const vlSymsp;
| ^~~~~~~
In file included from main.cpp:2:
testbench.h: In member function ‘virtual uint8_t testbench::read(uint32_t)’:
testbench.h:127:30: error: ‘struct Vriscv_tcm_top’ has no member named ‘__VlSymsp’; did you mean ‘Vriscv_tcm_top__Syms* const Vriscv_tcm_top::vlSymsp’? (not accessible from this context)
127 | return m_dut->m_rtl->__VlSymsp->TOP__v__u_tcm.read(addr);
| ^~~~~~~~~
In file included from testbench.h:12,
from main.cpp:2:
./verilated/Vriscv_tcm_top.h:26:33: note: declared private here
26 | Vriscv_tcm_top__Syms* const vlSymsp;
| ^~~~~~~
In file included from main.cpp:2:
testbench.h: In member function ‘virtual uint32_t testbench::get_opcode()’:
testbench.h:158:37: warning: no return statement in function returning non-void [-Wreturn-type]
158 | uint32_t get_opcode(void) { }
| ^
make[1]: *** [makefile.build_sysc_tb:56: obj/main.o] Error 1
make[1]: Leaving directory '/home/alan/riscv/top_tcm_axi/tb'
make: *** [makefile:30: build] Error 2
---------------------------------Briefly speaking--------------------------------------
The main error message is :
testbench.h:111:23: error: ‘struct Vriscv_tcm_top’ has no member named ‘__VlSymsp’; did you mean ‘Vriscv_tcm_top__Syms* const Vriscv_tcm_top::vlSymsp’? (not accessible from this context)
111 | m_dut->m_rtl->__VlSymsp->TOP__v__u_tcm.write(addr, data);

I try to use replace __VlSymsp with vlSymsp but got error said "vlSymsp is private"
I am wondering if it is caused by the different version of verilator?

Could anyone help me with this error?

May I ask by which tools you draw the sequential diagram?

May I ask by which tools you draw the sequential diagram in the README file :)

run elf file

i tried to run an elf file with isa-simulator and i faced the 000101b4: Bad memory access 0xfffffff8 error. i want to know which command (with options) did you used to compile c file to elf (i tried various type of options but it didn't work)?‌

verilator version

Your project has strict requirements on the version of Verilator. Due to the changes in translation rules of the new version of Verilator, it cannot be directly applied to your project. Even if I specifically changed “tb” to make “make” pass, I still had problems with “make run”. However, when I switched to an older version of Verilator 4.028, everything was fixed.

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