The image convolution operation is used in a variety of applications. Sometimes, these applications require real-time processing and using hardware accelerators can be a good way for achieving this. Hardware accelerators can be implemented on Graphics Processing Units (GPU’s) or Field Programmable Gate Arrays (FPGA’s).

In this project, a 2D Image Convolution Filter was implemented in an FPGA with the purpose of filtering 8-bit grayscale images. The convolution architecture design was based on a previous work presented as a thesis and can be found in [1]. The hardware description is done using VHDL and simulations where performed using ModelSim software. The results were satisfactorily obtained and evaluated by looking at the output images. No quantitative evaluation was performed, as it is not necessary for this project.

[1] Henrik Ström, ”A Parallel FPGA Implementation of Image Convolution” Department of Electrical Engineering, Linköping University, Sweden, 2016.