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💾 Improvement to a MIPS processor simulation written in Java. Benchmarks used to track improvements of specific changes

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mips-assembly mips-architecture mips-simulator pipeline-processor

mips-processor-simulation's Introduction

MIPS-Processor-Simulation

The proposed project is to explore the effects of different cache structures on the read, write and overall average memory access time as well as the total number of stalls in the pipeline due to structural hazards caused by the memory module. The simulator that was modified is EduMIPS64

Repository Structure

The Benchmarks folder is as was provided to us, while the remainder is the actual edumips64 implementation.

All configuration JSON files used for testing can be found in cache_config/configs/ and the resulting JSON files corresponding to these tests can be found in cache_config/results/. The majority of the cache implementation code is located in edumips64/cache/, and the ui adjustments were done in the main class like the other buttons.

The python/ folder contains all the jupyter notebooks used for calculating the results and generating the graphs of the cache behaviour.

Cache Abstraction Class Diagram

Below is the class diagram of the new module that was developed to simulate a cache. TheCacheMan-ageris the most important class were most of the calls from the existing system go through. thesetupmethod can ingest the file path of the JSON configuration file which will create a set ofDirectMapped-CacheLayerandSetAssociativeCacheLayerobjects that represents the configuration. Later on, whenmemory accesses are made, thecalculateLatencymethod is called to calculate how many cycles a parti-cluar access at a specific address takes with the current cache state.The only two concrete classes for Cache layers are theDirectMappedCacheLayerand theSetAssociative-CacheLayerwhich have different internal mechanics for placing and replacing blocks. However both ofthese classes implement theICacheLayerinterface which concists of all methods needed by theCache-Managerto calculate the memory latency for the whole cache structure. The general fields shared amongall types of caches are stored in theCacheLayerabstract class.Lastly, theCacheBlockis the abstraction for a block in the cache. It is contained by theCacheLayerclass so that it can keep track of all the block currently in that layer and the validity of each block.SetAssociativeCacheLayeruses thePriorityCacheBlockto keep track of what to evict next with respectto its eviction policy.

Results found

For each test, a particular parameter of the cache was changed in an isolated way. The results can be seen in the /pyhon folder of the improved repository. The metric that is observed is the average memory access time measured in clock cycles.

Comparing the associativity (From direct mapping to Fully associative)
Comparing the cache size to block size ratio
Comparing the number of levels in the cache
Comparing the replacement policies (For Fully and set associative)
Comparing the write strategies (write through and write back)

How to load a new cache configuration and export statistics

1. Load the configuration file

2. Load the simulation file

3. Run the simulation

F4 for running te whole progream F7 for single step

4. Export statistics

5. Either: Clear the current cache config or load a new config

Format of configuration file

There are certain parameters that are required to load a cache configuration, such as mmat and caches. Caches can be left as an empty list if there are no caches in the specified configuration. However, if there is a cache object then the following parameters that will need to be provided are size, blockSize, accessTime, mappingScheme and writeStrategy. Size and blockSize have to be powers of 2, must have a postfix of B, KB or MB to indicate bytes, kilobytes or megabytes and must have a blockSize smaller or equal to size. AccessTime should preferably for a cache be smaller than the main memory access time. For mappingScheme the options are:

DIRECT
N_WAY_SET_ASSOCIATIVE_LRU (where N is an integer multiple of 2)
N_WAY_SET_ASSOCIATIVE_FIFO
N_WAY_SET_ASSOCIATIVE_RANDOM
FULLY_ASSOCIATIVE_LRU
FULLY_ASSOCIATIVE_RANDOM
FULLY_ASSOCIATIVE_FIFO

Lastly for writeStrategy, the available options are:

WRITEBACK (which uses a write back write allocate strategy)
WRITETHROUGH (which uses a write through no write allocate strategy)

Format of the result files

The result file contains all the information that was already in the configuration file such that the user can see what the configuration that was used for the run. The name of the benchmark file that the test ran on is also included as benchmark_name. Additionally, the average memory access time overall, for read accesses, and for write accesses (amat, amat_read, amat_write} respectively). Finally, The hit rate of each cache layer is present so that the user can identify were the bottleneck is when the average memory access time is higher than expected.

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mips-processor-simulation's Issues

Write a parser class to read in the configuration JSON file

When the user will configure his cache, the file they selected will go through this parser and create the cache objects to be stored in the Memory class.
This shouldnt do all this extra stuff, just a method that takes in the file path then creates a list of caches based on that.
We should also find a way to return the main memory access time as well.
Remember to throw some exceptions as well. Whoever calls this will have to catch them

Bug in loading json

If you load config, run, export, then load a new config, the new config doesnt get registered properly. I think it might be an issue with needing to reset the Cachemanager before doing setup again, easy fix will do tonight or tomorrow.

Write a python script that can parse through many stats file and generate us some nice graphs

We can generate many stats file and the python script can take those in and generate some nice graphs so we can visualize the data

Modify UI to show Memory stalls statistic

Just an extra field with all the other stats
Make a way to make it invisible as well. for when we run the ap normally. And it appears when we go in the Real-Cache mode

Change the format of results file

The result file should have more things

{
  "mmat" : 50,
  "totalStalls" : 1365,
  "benchmark" : "<benchmarkFileName>"
  "caches" : [
    {
      "size" : "64B",
      "blockSize" : "8B",
      "accessTime" : 5,
      "mappingScheme" : "4_WAY_SET_ASSOCIATIVE_LRU",
      "writeStrategy" :  "WRITE_BACK",
      "hitRate" = 0.24
    },
    {
      "size" : "128B",
      "blockSize" : "16B",
      "accessTime" : 15,
      "mappingScheme" : "FULLY_ASSOCIATIVE_FIFO",
      "writeStrategy" :  "WRITE_THROUGH",
      "hitRate" = 0.76
    }
  ]
}

This way we keep track of more things for when we feed these files to the python scripts

We could extend the mini class CacheLayerConfig in CacheManager to so that we can add an extra fleid called hitRate. That object can then be serrialized to a JSON with the json jar library.
The benchmark name and main memory access time should also be included in the result file

Make a "Save cache statistics" button to export the stats at the end of a run will be useful for #4

I'm gonna make a button with a file selection/saving window so we can choose where to save and what name to use, once the stats writing is implemented we should be able to plug & play

Bug: Mem Stall count not resetting properly

When we reset the program, the memory stall count does not reset to 0

Make a utility class that can write the stats to a file

Stats should be written to a file when a button is pressed (Just like a button wherever in the screen always enabled).
Format can be CSV with nice labels, or JSON/XML

Also the user should ideally chose where they are writing this file

Make sure that the configuration is somehpw saved here too so we know what the cache setup was for those stats

Update CPU lock cycles when updating the MemoryStalls count

Right now we only update the stall count without updating the number of total clock cycles. We end up with more stall cycles than the total number of CC

Create a fully associative cache layer class

We could have a Fully associative cache layer class that would be nice

Create domain objects

CacheManager
Cache
CaheEmelent

Add graphs for hit rates vs cache size for particular benchmarks

Display error messages with the ErrorDialog class

When something goes wrong when loading the JSON config we want to display that to the user with a dialog displaying the exception message

Integrate a SetAssociativeCacheLayer class

We can use this class with setSize = num cache blocks to do fully associative

Write logic to allow WriteBack strategy for some layers

The calculateDelay() method in the CacheManager calls the read or write to cache methods, we want to allow some caches to use the write through strategy

When loading a new program, disable the cache. Enable it once the program is loaded

since when setting up, the stall count is incremented before the program starts

What we want is that when we load the program, the stall count for memory is 0

Add AMAT for read write and overall vs cache schemas used

Add more statistics such as hit rate of specific caches

We should probably add stats for the hit rates of caches so we can show that FA has a better hit rate?

Write the calculateDelay() interface in the CacheManager class

This is the big task. This will go through all the caches to find out where we miss and where we hit.
It should also update the caches if it is a miss and evict correctly and write to lower layer if it was dirty

Create an extra button in the File drop down menu to Configure cache

Make sure that this button is only enabled when the processor has just been reset. Otherwise we should not be able to change our cache configuration mid execution

Make a button to reset cache configs to default

Under the loadJSON button in the Cache config tab makse a button Reset which resets the cache config to 0 latency.

basically just call cachemanager.reset()

Dont forget to disable the busson once the program is started. should only be accessible when we are at the start of the program

Integrate the logic for the memory class to call the Cache manager whenever there is a memory access

Whenever there is a memory access in the Memory class, we want to calculate that delay. This stands both for instructionsFetch and getCell().

When getCell is called we want a new argument indicating if the access is indented to read or write to memory

When the delay is calculated, we want to update the memory stalls stats