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lenet's Introduction

Hi there

  • This account is primarily for Intel internal projects, so there will not be many public commits. There are also some repositories from my university days that are no longer maintained. They should be free to use, but please check the license for the collaboration repositories;
  • If you have any questions, you can reach out to my personal email ([email protected]), but please expect infrequent or no responses since these projects are from several years ago, thanks for your understanding;
  • In general, I'm a hardware-focused engineer currently working on Intel server platform customized solutions. My work mainly involves FPGA/CPLD solutions, power sequence details, server platform design methodologies and implementation, and system debugging on both hardware and firmware. So I frequently use Verilog, and also write some C/C++/Python scripts, mostly out of interests.

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lenet's Issues

some question to

I want to ask, is this code applied in the end? Can it be integrated into vivado block design, and share the engineering code?

in dnn.cpp

  • There is a problem with the calculation process, and the final accuracy is only 0.08.

Consider code correctness or data type.

Optimization

The default Interval is 90000+, we want it smaller than 150.
And if I change the loops as PIPELINE, it reduced to about 5000, but clock period is 8.95 ns.

in Simulation 1.1

WARNING

  • HLS only supports CLANG compiler in Linux;

ERROR

  • CSim failed with errors;
  • Open txt error in reading bias and weights@E Simulation failed.

I don't know why. May be code problem or problem during simulation in HLS.
Leave a note when the problem is resolved.

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