CURRENT STATUS : stable

• A generic trace driven cache simulator of last level Cache for a new processor that can be used with up to three other processors in a shared memory configuration.
• It employs a write allocate policy and uses the MESI protocol to ensure coherence.
• The replacement policy is implemented with a true-LRU scheme.
• The simulator was configurable in terms of cache size, block size and associativity.

Download all the project files into your local system.

Mentor Questasim\Modelsim

Step by step instructions to setup the project in your local machine

• Open the directory in your local machine which contains all files of the project
• Open terminal with the same directory

• Execute make command in the command line which will execute all_traces.txt trace file
• For executing other trace files use - make trace_name=<Trace file name>

• Compiles
• Change Cache parameters during runtime
• Change input Trace file during runtime
• Simulated CPU reads
• simulated CPU writes
• Simulated Snoop reads
• Simulated Snoop writes
• Simulated Snoop RWIM
• Simulated Snoop Invalidate

This project has been developed with Mentor Questasim.

• Vinod Sake - Initial work - Github
• Kundan Vanama

This project is licensed under the open-source license