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core_usb_cdc

Basic USB-CDC device core (Verilog)

debug-mechanism-comparison

Comparison of 2 proposed debug mechanisms.

educational-materials

Educational materials for RISC-V

esp-idf

Espressif IoT Development Framework. Official development framework for Espressif SoCs.

fossi-research

fusesoc

fusesoc-docker

Just a set of Dockerfiles and tools for FuseSoC

fusesoc-templates-demo

Demo files for FuseSoC templates

fusesoc.github.io

fusesoc_cores

gfmpw-1

glabs

Manage GitLab for Labs from the Command Line

glip

Generic Logic Interfacing Project

grammars-v4

Grammars written for ANTLR v4; expectation that the grammars are free of actions.

hm-asm

A small assembler I wrote for use with the microprocessor from the Book "Grundlagen der Technische Informatik"

home-assistant.io

:blue_book: Home Assistant User documentation

hugo-academic

📝 The website builder for Hugo. Build and deploy a beautiful website in minutes!

hugo-serif-theme

Serif is a modern business theme for Hugo.

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

ics2ews

Synchronize ICS to Exchange

jenkins-pipeline-yaml

l4linux

L4Linux

linux

OpenRisc Spinoff of Linux

lk

LK embedded kernel

lowrisc-chip

The root repo for lowRISC project and FPGA demos.

lowrisc-fpga

Untethered (stand-alone) FPGA implementation of the lowRISC SoC

lowrisc-nexys4

FPGA demo for Digilent NEXYS 4 board

lowrisc-site

lowrisc-untether

lowRISC: Untethered Rocket on KC705 (and other FPGA boards)

lttng-ust

This repo is a mirror of the official lttng-ust git found at git://git.lttng.org/lttng-ust.git. LTTng-UST, the Linux Trace Toolkit Next Generation Userspace Tracer, is port of the low-overhead tracing capabilities of the LTTng kernel tracer to user-space. The library "liblttng-ust" enables tracing of applications and libraries.