计划写的流水线处理器
C++实现的处理器模型 用于与处理器RTL模型混合仿真
Verilog实现的单周期处理器模型 Verilator仿真通过
汇编编写的基本测试程序 复杂一些的C语言程序,但是还是测试不充分,更复杂的程序后面再说
SV实现 Verilator仿真通过
yosys综合 移植到vcs上 vivado综合 尝试DC综合
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