Comments (11)
In a few minutes I will make corrections in nextpnr and the networks will be routed correctly.
In the meantime, one question: are you sure that your design will show something on the screen? I ask because I have a white screen and if you are confident in the design, then the problems with the networks are much deeper than I thought.
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I looked at the generated signals:
Sorry for not changing the label, but the connection is this:
channel 0 - pin 35 LCD_LCK
channel 1 - pin 34 LCD_SYNC
channel 2 - pin 33 LCD_DEN
channel 3 - pin 40 LCD_HYNC
The apicula: LCD_CLK 9MHz, a very beautiful and uniform vertical sync signal ~ 58 frames per second.
my.mp4
Gowin option - LCD_CLK is also 9MHz, but instead of a vertical sync signal there is terror that flaps in the night.
gw.mp4
My display just canโt handle such tricks, so I think there are no errors in software just different displays - your display can work with such vertical sync, but mine can't. You can close the issue. ๐
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Yes, it should look like this one:
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hmm... this is their picture, but have you tried compiling this project in the IDE?
Or just download their ready-made .fs and flash it in Tangnano9k?
https://github.com/sipeed/TangNano-9K-example/tree/main/lcd_4.3
Perhaps my board just died completely.
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If you have the apicula repository installed, then you can now assemble the example bsram-SDPB-tangnano9k.fs which is more beautiful and everything is fine with VGA and wires ๐
cd wherever-you-installed-the-apicula-repository/apicula/examples/himbaechel
make -f Makefile.himbaechel bsram-SDPB-tangnano9k.fs
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make -f Makefile.himbaechel bsram-SDPB-tangnano9k.fs
This works the the two little spirits show up on my LCD. (with a Mac with M2 chip)
have you tried compiling this project in the IDE?
Yes, I did compiled the source with Gowin IDE on Windows and it works (never used their fs file).
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If you donโt want to compile nextpnr yourself, then remove references to all unused PLL outputs like .CLKOUTP and your project will compile right now.
It's strange that in my case everything is white...
from apicula.
Thanks @yrabbit for the help!
I'll try compile later today using the branch you drafted.
Had a quick skim on command in Makefile.himbaechel
, it involves some vh
files in, but there seems no corresponding thing in my pll, not sure if it is because of the Gowin IP thing does not "linked" or not.
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Well, apicula is designed for many boards with different quartz and therefore the PLL parameters are placed in separate files.
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I tried your nextpnr branch, it works! Thanks for your time @yrabbit
I noticed there are some noise in the LCD with apicula, compared to Gowin compiled. But the fs apicula produced is good enough.
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Oh, this is quite expected - in your first message it is indicated that the router cannot route from the PLL output to X33Y8/A6. Here the destination is not a clock input or IO pin and such networks are currently given to the general purpose router. Perhaps in the future I will complicate the dedicated router or not - I somehow donโt really like using the clock as an input for the LUT ๐
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Related Issues (20)
- Question - how to include last commits of apicula in nextpnr HOT 6
- FPGA initialises but doesn't run. Same code works on the vendor tools. HOT 9
- GW5A family support HOT 4
- GW1NR-9 vs GW1N-9 bit-stream HOT 12
- Tang nano 20k support HOT 23
- CLKDIV support HOT 13
- gowin_pack fails with "'GW1NR-UV9QN881C6/I5.pickle' must be only a file name" HOT 3
- Simple blinky does not work on tangnano9k HOT 4
- szfpga board support HOT 2
- Please use a crc library that provides a pure Python implementation HOT 5
- Incompatible with Python 3.8
- Better documentation for Sipeed nano 20k support HOT 8
- Move away from numpy HOT 7
- gowin_pack hangs on OSER10 - ELVDS_OBUF combo on Tang Nano 9K HOT 6
- Optimistic compression approach HOT 3
- PLL unstable on tec0117 HOT 1
- MULT36x36 not working, but MULT18x18 is working! - DSP Primitive HOT 2
- Cant find how to compile for tang nano 20k HOT 6
- Tang Nano 9k: rPLL is not working at all HOT 6
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