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License: MIT License
Project Apicula π: bitstream documentation for Gowin FPGAs
License: MIT License
After updating from v0.0.1a11 to v0.0.1a12 nextpnr-gowin fails to execute the JSON backend.
Args:
yosys -p "synth_gowin -json synth.json" top.v
nextpnr-gowin --json synth.json --write design.json --device GW1N-LV1QN48C6/I5 --cst tangnano.cst
Error:
4.29. Executing JSON backend.
Warnings: 770 unique messages, 770 total
End of script. Logfile hash: 4236f24c6b, CPU: user 1.44s system 0.02s, MEM: 55.97 MB peak
Yosys 0.10+1 (git sha1 7a7df9a3b4, gcc 10.3.0 -fPIC -Os)
Time spent: 27% 1x abc (0 sec), 22% 3x techmap (0 sec), ...
ERROR: Unsuported speed grade 'C6/I5'.
0 warnings, 1 error
This fails for even a simple LED blinky design, top.v
:
(* top *)
module TOP
(
input rst,
input clk,
output LCD_CLK,
output LCD_HYNC,
output LCD_SYNC,
output LCD_DEN,
output [4:0] LCD_R,
output [5:0] LCD_G,
output [4:0] LCD_B,
output [7:5] led
);
wire CLK_SYS;
wire CLK_PIX;
wire LED_R;
wire LED_G;
wire LED_B;
assign CLK_SYS = clk;
assign CLK_PIX = clk;
assign led[5] = LED_R;
assign led[6] = LED_G;
assign led[7] = LED_B;
// RGB LED TEST
reg [31:0]cnt;
reg [1:0]rgb_data;
always @( posedge CLK_SYS or negedge rst )
begin
if (!rst) begin
cnt <= 32'd0;
rgb_data <= 2'b00;
end
else if (cnt == 12000000) begin
cnt <= 4'b0;
rgb_data <= rgb_data + 1'b1;
end
else
cnt <= cnt + 1'b1;
end
assign LED_R = ~(rgb_data == 2'b01);
assign LED_G = ~(rgb_data == 2'b10);
assign LED_B = ~(rgb_data == 2'b11);
endmodule
I just bought a Tang Nano 1K board, which to my surprise, was not the same thing as Tang nano. The Tang Nano 1K board has a GW1NZ-1 chip instead of GW1N-1 so naturally the examples don't work on the new board. Is the GW1NZ-1 chip already supported by project apicula and nextpnr-apicula so that the example designs could be ported to this board as well?
FYI
On my Tang Nano, when I did all of this.
cd examples
yosys -p "synth_gowin -json blinky.json" blinky.v
nextpnr-gowin --json blinky.json \
--write pnrblinky.json \
--device GW1NR-UV9QN881C6/I5 \
--cst tec0117.cst
gowin_pack -d GW1N-9 -o pack.fs pnrblinky.json
# gowin_unpack -d GW1N-9 -o unpack.v pack.fs
# yosys -p "read_verilog -lib +/gowin/cells_sim.v; clean -purge; show" unpack.v
openFPGALoader -b tangnano pack.fs # Tang Nano
I could not get it to finish loading. I tried a bunch of stuff. I even replaced the firmware of the CH552 chip.
Anyway, after a lot of flailing and reading, I tried some other .fs (from https://github.com/racerxdl/tangnano-yosys-hello)
and that worked fine.
After that, in apicula/examples, I did a full make. Then, this one worked
openFPGALoader -b tangnano blinky-tangnano.fs
So, maybe "pack.fs" isn't what should be on the main README?
I'm using virtualenv version to use python 3.7 :
$ source ~/pyenv/pyenv37/bin/activate
$ python --version
Python 3.7.5
But nextpnr use python 3.5 to run python script given in argument:
$ echo "import sys;print(sys.version)" > version.py
$ nextpnr-generic --run version.py
3.5.3 (default, Sep 27 2018, 17:25:39)
[GCC 6.3.0 20170516]
Is it a compile option for nextpnr ? Or can I change it with environment vars ?
3.5 is too old for executing simple.py script in fact (f-string problem).
nextpnr-generic --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
File "simple.py", line 18
with open(f"../{device}.pickle", 'rb') as f:
^
SyntaxError: invalid syntax
ERROR: Error occurred while executing Python script simple.py
0 warnings, 1 error
I keep trying, but if you have a clue ;)
I've been trying to build my_hdmi_device by splinedrive with apicula and have gotten pretty far along with some tweaks.
gowin_pack with the current apicula/chipdb fails with this strange error on the nano9k
gowin_pack -d GW1N-9C -o chip_balls.fs chip_balls_pnr.json
Traceback (most recent call last):
File "/opt/homebrew/bin/gowin_pack", line 8, in <module>
sys.exit(main())
File "/opt/homebrew/lib/python3.10/site-packages/apycula/gowin_pack.py", line 703, in main
place(db, tilemap, bels, cst, args)
File "/opt/homebrew/lib/python3.10/site-packages/apycula/gowin_pack.py", line 452, in place
raise Exception(f"Different I/O modes for the same bank {bank} were specified: {iostd} and {flag_name_val[1]}")
Exception: Different I/O modes for the same bank 1 were specified: LVCMOS18 and LVCMOS33
make: *** [chip_balls.fs] Error 1
Steps to reproduce
git clone https://github.com/martell/my_hdmi_device
cd my_hdmi_device
git checkout yosys-nano9k
make -f Makefile.nano9k
@yrabbit @pepijndevos This seems very close since merging #156
Is there any plans to support the Tang Nano 9k board?
How to use apicula on GW1NSR-4C chip with or without Cortex-M3 support?
I was trying to use the Open source PSRAM module (https://github.com/zf3/psram-tang-nano-9k)
However that module uses the IDDR module which doesn't seem to exist in Yosys/apicula.
Can we add support for the IDDR module? (Or maybe a pointer on how I can help implement this for apicula?)
Thanks!
Just recieved my tangnano9k and tried to upload simple led demos.
Below script runs 100% ok except for the bitstream upload... It seem the bitstream generated is for different device...
yosys -D LEDS_NR=8 -p "read_verilog blinky.v; synth_gowin -json blinky.json"
DEVICE='GW1NR-LV9QN88PC6/I5' # change to your device
BOARD='tangnano9k' # change to your board
nextpnr-gowin --json blinky.json \
--write pnrblinky.json \
--family GW1N-9C \
--device $DEVICE \
--cst $BOARD.cst
gowin_pack -d $DEVICE -o pack.fs pnrblinky.json # chango to your device
# gowin_unpack -d $DEVICE -o unpack.v pack.fs
# yosys -p "read_verilog -lib +/gowin/cells_sim.v; clean -purge; show" unpack.v
openFPGALoader -v -b $BOARD pack.fs
results in:
Yosys 0.18+29 (git sha1 b2408df31, clang 13.0.1 -fPIC -Os)
Time spent: 38% 10x read_verilog (0 sec), 12% 13x opt_clean (0 sec), ...
+ DEVICE=GW1NR-LV9QN88PC6/I5
+ BOARD=tangnano9k
+ nextpnr-gowin --json blinky.json --write pnrblinky.json --family GW1N-9C --device GW1NR-LV9QN88PC6/I5 --cst tangnano9k.cst
...
Info: Program finished normally.
+ gowin_pack -d GW1NR-LV9QN88PC6/I5 -o pack.fs pnrblinky.json
+ openFPGALoader -v -b tangnano9k pack.fs
Jtag frequency : requested 6.00MHz -> real 6.00MHz
found 1 devices
index 0:
idcode 0x100481b
manufacturer Gowin
family GW1N
model GW1N(R)-9C
irlength 8
File type : fs
Parse file Parse pack.fs:
checksum 0x3625
Done
DONE
bitstream header infos
CRCCheck: ON
Compress: OFF
ConfDataLength: 712
ProgramDoneBypass: OFF
SPIAddr: 00fff000
SecurityBit: ON
idcode: 1100581b
loading_rate: 0
BTW, what does the name mean?
In the readme.md of apicula:
https://github.com/YosysHQ/apicula/blob/master/readme.md
yosys -D LEDS_NR=8 -p "synth_gowin -json blinky.json" blinky.v
This works fine with yosys 0.12. since yosys 0.13, yosys need to have the read_verilog instruction to work and the verilog files are passed to it instead of the end of the line:
yosys -D LEDS_NR=8 -p "read_verilog blinky.v; synth_gowin -json blinky.json"
Both syntax depending on version should so be described.
I'm totally new to this so forgive me if I don't use the correct terminology (and feel free to rephrase the title to make it clearer :)
I have this:
module counter
(
input clk,
output [5:0] led
);
localparam WAIT_TIME = 13500000;
reg [5:0] ledCounter = 4;
reg [23:0] clockCounter = 0;
always @(posedge clk) begin
clockCounter <= clockCounter + 1;
if (clockCounter == WAIT_TIME) begin
clockCounter <= 0;
ledCounter <= ledCounter + 1;
end
end
assign led = ~ledCounter;
endmodule
and this .cst
file:
IO_LOC "clk" 52;
IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP;
IO_LOC "led[0]" 10;
IO_PORT "led[0]" DRIVE=8 IO_TYPE=LVCMOS18;
IO_LOC "led[1]" 11;
IO_PORT "led[1]" DRIVE=8 IO_TYPE=LVCMOS18;
IO_LOC "led[2]" 13;
IO_PORT "led[2]" DRIVE=8 IO_TYPE=LVCMOS18;
IO_LOC "led[3]" 14;
IO_PORT "led[3]" DRIVE=8 IO_TYPE=LVCMOS18;
IO_LOC "led[4]" 15;
IO_PORT "led[4]" DRIVE=8 IO_TYPE=LVCMOS18;
IO_LOC "led[5]" 16;
IO_PORT "led[5]" DRIVE=8 IO_TYPE=LVCMOS18;
Building and loading this on a Tang Nano 9k (make load
) worked fine using the 2022-12-15 release. The leds are changing as ledCounter
is increased.
However, if I build and load this using the 2022-12-16 release it loads correctly, but the leds are not changing. One led is turned on (as ledCounter
is initiated with 4).
It's like the whole always posedge clk
block isn't there.
Comparing the build files i noticed the generated _pnr.json
files differs between versions, and of course the bitstream differs.
I'm running the darwin-arm64 versions.
Here is the source code and generated files for each release version
counter_2022-12-15.zip
counter_2022-12-16.zip
Let me know if you need any more info.
Hi Apicula authors,
I'd like to cross-reference your experience regarding a board stability issue that I am seeing to affect Gowin's FPGAs when using Gowin's own tools.
Check out https://github.com/juj/gowin_flipflop_drainer/ and https://www.reddit.com/r/FPGA/comments/101pagf/sipeed_tang_nano_4k_9k_gowin_fpgas_become/ for details.
I am wondering if there have been anything similar happening in your experience?
Using OSS CAD Suite, with:
Yosys 0.24+1 (git sha1 7ad7b550c, x86_64-apple-darwin20.2-clang 10.0.0-4ubuntu1 -fPIC -Os)
Apycula 0.5.2.dev3+g16a91ef
GHDL 3.0.0-dev (2.0.0.r515.g780165a75) [Dunoon edition]
the attached simple SPI display module ends up sending one additional byte during initialization (the first byte of the initialization sequence is sent one more time at the end) if the condition on line 142 is:
if init_byte_index < oled_init'length then
if the <
is changed to /=
there is no issue. This does not reproduce in simulation (simple testbench also attached). It also does not reproduce with Gown's tools (same source, with the less-than comparison <
). Observed on device using a logic analyzer.
I'm not sure if this bug report belongs here, yosys
, nextpnr
, or elsewhere; but given the behaviour difference compared to Gowin's tools I figured it's worth filing.
screen_tb.vhd.txt
screen.vhd.txt
tangnano9k.cst.txt
I've attached the cst file in use as well to reproduce; the pins in question are also listed below, and no display should be needed to observe:
IO_LOC "io_cs" 36;
IO_LOC "io_dc" 39;
IO_LOC "io_rst" 25;
IO_LOC "io_sdin" 26;
IO_LOC "io_sclk" 27;
Hi,
It seems like apicula currently doesn't support the hardware DSP capabilities [UG287E.pdf] 1 of Gowin FPGA chips.
I'm not currently interested in automatic inference of DSP modules based on higher level Verilog code but I'm looking for a way to manually instantiate MULT18X18 blocks etc.
Am I missing anything?
Thanks a lot for your efforts.
Hello,
there are any plans to support the new Tang Primer 20k board (GW2A-LV18PG256C8/I7)?
As far as I can see, we don't have any GW2A support yet. Could we discuss the steps required to get this included? I have the hardware and would be willing to help.
Thanks.
The instructions to run the blinky example appear to be broken.
After I run yosys -p "synth_gowin -json blinky.json" blinky.v
I get this error:
Yosys 0.9+4276 (git sha1 75a4cdfc8a, gcc 10.3.0 -fPIC -Os)
-- Parsing `blinky.v' using frontend `verilog' --
1. Executing Verilog-2005 frontend: blinky.v
Parsing Verilog input from `blinky.v' to AST representation.
blinky.v:3: ERROR: Unimplemented compiler directive or undefined macro `LEDS_NR.
This appears to be broken due to this commit: ecfdeb9
Normally I would offer a PR to fix this but I am still learning verilog/FPGAs, and I do not know how this should be corrected.
Thanks for this project!
@whitequark informed me that YoWASP build recently broke and @gatecat said it might help to run it in valgrind to see if the error reproduces.
YoWASP/nextpnr@461a69a#commitcomment-91992429
Relatedly, our own YoWASP CI has also been broken for a while, which just one day a couple of months stopped working. This however seems like a different error, possibly just incompatible nextpnr and apicula versions. https://github.com/YosysHQ/apicula/actions/workflows/yowasp_examples.yml
Anyway I've run nextpnr in valgrind and this is the result. An invalid read in some json code that was allocated and freed in the timing analyzer? Haven't looked deeper into it, just want to dump the output somewhere before I go to bed. It took quite a while to run it under valgrind...
==36158== Invalid read of size 4
==36158== at 0x29FCBD: UnknownInlinedFun (jsonwrite.cc:91)
==36158== by 0x29FCBD: nextpnr_gowin::JsonWriter::write_module(std::ostream&, nextpnr_gowin::Context*) (jsonwrite.cc:132)
==36158== by 0x337C55: UnknownInlinedFun (jsonwrite.cc:210)
==36158== by 0x337C55: UnknownInlinedFun (jsonwrite.cc:223)
==36158== by 0x337C55: nextpnr_gowin::CommandHandler::executeMain(std::unique_ptr<nextpnr_gowin::Context, std::default_delete<nextpnr_gowin::Context> >) [clone .constprop.0] (command.cc:475)
==36158== by 0x15ACE4: UnknownInlinedFun (command.cc:533)
==36158== by 0x15ACE4: main (main.cc:113)
==36158== Address 0x44caac60 is 0 bytes inside a block of size 92 free'd
==36158== at 0x4844B5F: operator delete(void*, unsigned long) (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==36158== by 0x237F2A: UnknownInlinedFun (new_allocator.h:158)
==36158== by 0x237F2A: UnknownInlinedFun (alloc_traits.h:496)
==36158== by 0x237F2A: UnknownInlinedFun (stl_vector.h:387)
==36158== by 0x237F2A: UnknownInlinedFun (stl_vector.h:366)
==36158== by 0x237F2A: UnknownInlinedFun (stl_vector.h:733)
==36158== by 0x237F2A: UnknownInlinedFun (hashlib.h:212)
==36158== by 0x237F2A: UnknownInlinedFun (timing.h:175)
==36158== by 0x237F2A: UnknownInlinedFun (stl_pair.h:185)
==36158== by 0x237F2A: UnknownInlinedFun (hashlib.h:214)
==36158== by 0x237F2A: UnknownInlinedFun (stl_construct.h:151)
==36158== by 0x237F2A: UnknownInlinedFun (stl_construct.h:163)
==36158== by 0x237F2A: UnknownInlinedFun (stl_construct.h:196)
==36158== by 0x237F2A: UnknownInlinedFun (alloc_traits.h:850)
==36158== by 0x237F2A: UnknownInlinedFun (stl_vector.h:730)
==36158== by 0x237F2A: UnknownInlinedFun (hashlib.h:212)
==36158== by 0x237F2A: nextpnr_gowin::TimingAnalyser::~TimingAnalyser() (timing.h:73)
==36158== by 0x283315: UnknownInlinedFun (router1.cc:101)
==36158== by 0x283315: nextpnr_gowin::router1(nextpnr_gowin::Context*, nextpnr_gowin::Router1Cfg const&) (router1.cc:984)
==36158== by 0x2C8DFC: nextpnr_gowin::Arch::route() (arch.cc:2079)
==36158== by 0x338D2A: nextpnr_gowin::CommandHandler::executeMain(std::unique_ptr<nextpnr_gowin::Context, std::default_delete<nextpnr_gowin::Context> >) [clone .constprop.0] (command.cc:461)
==36158== by 0x15ACE4: UnknownInlinedFun (command.cc:533)
==36158== by 0x15ACE4: main (main.cc:113)
==36158== Block was alloc'd at
==36158== at 0x4842003: operator new(unsigned long) (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==36158== by 0x33E416: UnknownInlinedFun (new_allocator.h:137)
==36158== by 0x33E416: UnknownInlinedFun (alloc_traits.h:464)
==36158== by 0x33E416: UnknownInlinedFun (stl_vector.h:378)
==36158== by 0x33E416: std::vector<int, std::allocator<int> >::_M_fill_insert(__gnu_cxx::__normal_iterator<int*, std::vector<int, std::allocator<int> > >, unsigned long, int const&) [clone .constprop.0] (vector.tcc:575)
==36158== by 0x320E9D: UnknownInlinedFun (hashlib.h:246)
==36158== by 0x320E9D: UnknownInlinedFun (hashlib.h:355)
==36158== by 0x320E9D: UnknownInlinedFun (hashlib.h:512)
==36158== by 0x320E9D: nextpnr_gowin::TimingAnalyser::copy_domains(nextpnr_gowin::CellPortKey const&, nextpnr_gowin::CellPortKey const&, bool) [clone .constprop.0] (timing.cc:767)
==36158== by 0x22DC1A: nextpnr_gowin::TimingAnalyser::setup_port_domains() (timing.cc:238)
==36158== by 0x22F377: nextpnr_gowin::TimingAnalyser::setup() (timing.cc:41)
==36158== by 0x281D26: UnknownInlinedFun (router1.cc:127)
==36158== by 0x281D26: nextpnr_gowin::router1(nextpnr_gowin::Context*, nextpnr_gowin::Router1Cfg const&) (router1.cc:871)
==36158== by 0x2C8DFC: nextpnr_gowin::Arch::route() (arch.cc:2079)
==36158== by 0x338D2A: nextpnr_gowin::CommandHandler::executeMain(std::unique_ptr<nextpnr_gowin::Context, std::default_delete<nextpnr_gowin::Context> >) [clone .constprop.0] (command.cc:461)
==36158== by 0x15ACE4: UnknownInlinedFun (command.cc:533)
==36158== by 0x15ACE4: main (main.cc:113)
==36158==
==36158== Warning: set address range perms: large range [0x59c8e028, 0x7dc8e058) (noaccess)
Info: Program finished normally.
==36158==
==36158== HEAP SUMMARY:
==36158== in use at exit: 141,445 bytes in 590 blocks
==36158== total heap usage: 31,851,461 allocs, 31,850,871 frees, 78,812,928,388 bytes allocated
==36158==
==36158== 8 bytes in 1 blocks are definitely lost in loss record 79 of 563
==36158== at 0x4842003: operator new(unsigned long) (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==36158== by 0x1E2119: UnknownInlinedFun (internals.h:505)
==36158== by 0x1E2119: pybind11::detail::get_local_internals() (internals.h:515)
==36158== by 0x33F37B: UnknownInlinedFun (type_caster_base.h:197)
==36158== by 0x33F37B: pybind11::detail::get_type_info(std::type_index const&, bool) [clone .constprop.0] (type_caster_base.h:218)
==36158== by 0x1DFC63: pybind11::cpp_function::initialize_generic(std::unique_ptr<pybind11::detail::function_record, pybind11::cpp_function::InitializingFunctionRecordDeleter>&&, char const*, std::type_info const* const*, unsigned long) (pybind11.h:436)
==36158== by 0x328557: UnknownInlinedFun (pybind11.h:297)
==36158== by 0x328557: UnknownInlinedFun (pybind11.h:100)
==36158== by 0x328557: pybind11::detail::enum_base::init(bool, bool) [clone .constprop.0] (pybind11.h:1933)
==36158== by 0x328ED7: pybind11::enum_<nextpnr_gowin::GraphicElement::type_t>::enum_<>(pybind11::handle const&, char const*) [clone .constprop.0] (pybind11.h:2153)
==36158== by 0x202F1C: nextpnr_gowin::pybind11_init_nextpnrpy_gowin(pybind11::module_&) (pybindings.cc:101)
==36158== by 0x20601F: UnknownInlinedFun (pybindings.cc:88)
==36158== by 0x20601F: pybind11_init_impl_nextpnrpy_gowin (pybindings.cc:88)
==36158== by 0x4BD0FF5: create_builtin (import.c:1012)
==36158== by 0x4BD1CD5: _imp_create_builtin (import.c:1063)
==36158== by 0x4B33D75: cfunction_vectorcall_O (methodobject.c:516)
==36158== by 0x4B297AF: UnknownInlinedFun (ceval.c:5915)
==36158== by 0x4B297AF: _PyEval_EvalFrameDefault (ceval.c:4277)
==36158==
==36158== 152 bytes in 1 blocks are definitely lost in loss record 428 of 563
==36158== at 0x4842003: operator new(unsigned long) (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==36158== by 0x201A66: pybind11::detail::generic_type::initialize(pybind11::detail::type_record const&) (pybind11.h:1304)
==36158== by 0x328EB7: UnknownInlinedFun (pybind11.h:1536)
==36158== by 0x328EB7: pybind11::enum_<nextpnr_gowin::GraphicElement::type_t>::enum_<>(pybind11::handle const&, char const*) [clone .constprop.0] (pybind11.h:2150)
==36158== by 0x202F1C: nextpnr_gowin::pybind11_init_nextpnrpy_gowin(pybind11::module_&) (pybindings.cc:101)
==36158== by 0x20601F: UnknownInlinedFun (pybindings.cc:88)
==36158== by 0x20601F: pybind11_init_impl_nextpnrpy_gowin (pybindings.cc:88)
==36158== by 0x4BD0FF5: create_builtin (import.c:1012)
==36158== by 0x4BD1CD5: _imp_create_builtin (import.c:1063)
==36158== by 0x4B33D75: cfunction_vectorcall_O (methodobject.c:516)
==36158== by 0x4B297AF: UnknownInlinedFun (ceval.c:5915)
==36158== by 0x4B297AF: _PyEval_EvalFrameDefault (ceval.c:4277)
==36158== by 0x4B34958: UnknownInlinedFun (pycore_ceval.h:46)
==36158== by 0x4B34958: UnknownInlinedFun (ceval.c:5065)
==36158== by 0x4B34958: _PyFunction_Vectorcall (call.c:342)
==36158== by 0x4B23B15: UnknownInlinedFun (abstract.h:114)
==36158== by 0x4B23B15: UnknownInlinedFun (abstract.h:123)
==36158== by 0x4B23B15: UnknownInlinedFun (ceval.c:5891)
==36158== by 0x4B23B15: _PyEval_EvalFrameDefault (ceval.c:4213)
==36158== by 0x4B34958: UnknownInlinedFun (pycore_ceval.h:46)
==36158== by 0x4B34958: UnknownInlinedFun (ceval.c:5065)
==36158== by 0x4B34958: _PyFunction_Vectorcall (call.c:342)
==36158==
==36158== 152 bytes in 1 blocks are definitely lost in loss record 429 of 563
==36158== at 0x4842003: operator new(unsigned long) (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==36158== by 0x201A66: pybind11::detail::generic_type::initialize(pybind11::detail::type_record const&) (pybind11.h:1304)
==36158== by 0x3294E7: UnknownInlinedFun (pybind11.h:1536)
==36158== by 0x3294E7: pybind11::enum_<nextpnr_gowin::GraphicElement::style_t>::enum_<>(pybind11::handle const&, char const*) [clone .constprop.0] (pybind11.h:2150)
==36158== by 0x202FAD: nextpnr_gowin::pybind11_init_nextpnrpy_gowin(pybind11::module_&) (pybindings.cc:110)
==36158== by 0x20601F: UnknownInlinedFun (pybindings.cc:88)
==36158== by 0x20601F: pybind11_init_impl_nextpnrpy_gowin (pybindings.cc:88)
==36158== by 0x4BD0FF5: create_builtin (import.c:1012)
==36158== by 0x4BD1CD5: _imp_create_builtin (import.c:1063)
==36158== by 0x4B33D75: cfunction_vectorcall_O (methodobject.c:516)
==36158== by 0x4B297AF: UnknownInlinedFun (ceval.c:5915)
==36158== by 0x4B297AF: _PyEval_EvalFrameDefault (ceval.c:4277)
==36158== by 0x4B34958: UnknownInlinedFun (pycore_ceval.h:46)
==36158== by 0x4B34958: UnknownInlinedFun (ceval.c:5065)
==36158== by 0x4B34958: _PyFunction_Vectorcall (call.c:342)
==36158== by 0x4B23B15: UnknownInlinedFun (abstract.h:114)
==36158== by 0x4B23B15: UnknownInlinedFun (abstract.h:123)
==36158== by 0x4B23B15: UnknownInlinedFun (ceval.c:5891)
==36158== by 0x4B23B15: _PyEval_EvalFrameDefault (ceval.c:4213)
==36158== by 0x4B34958: UnknownInlinedFun (pycore_ceval.h:46)
==36158== by 0x4B34958: UnknownInlinedFun (ceval.c:5065)
==36158== by 0x4B34958: _PyFunction_Vectorcall (call.c:342)
==36158==
==36158== 152 bytes in 1 blocks are definitely lost in loss record 430 of 563
==36158== at 0x4842003: operator new(unsigned long) (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==36158== by 0x201A66: pybind11::detail::generic_type::initialize(pybind11::detail::type_record const&) (pybind11.h:1304)
==36158== by 0x329B17: UnknownInlinedFun (pybind11.h:1536)
==36158== by 0x329B17: pybind11::enum_<nextpnr_gowin::PortType>::enum_<>(pybind11::handle const&, char const*) [clone .constprop.0] (pybind11.h:2150)
==36158== by 0x203414: nextpnr_gowin::pybind11_init_nextpnrpy_gowin(pybind11::module_&) (pybindings.cc:129)
==36158== by 0x20601F: UnknownInlinedFun (pybindings.cc:88)
==36158== by 0x20601F: pybind11_init_impl_nextpnrpy_gowin (pybindings.cc:88)
==36158== by 0x4BD0FF5: create_builtin (import.c:1012)
==36158== by 0x4BD1CD5: _imp_create_builtin (import.c:1063)
==36158== by 0x4B33D75: cfunction_vectorcall_O (methodobject.c:516)
==36158== by 0x4B297AF: UnknownInlinedFun (ceval.c:5915)
==36158== by 0x4B297AF: _PyEval_EvalFrameDefault (ceval.c:4277)
==36158== by 0x4B34958: UnknownInlinedFun (pycore_ceval.h:46)
==36158== by 0x4B34958: UnknownInlinedFun (ceval.c:5065)
==36158== by 0x4B34958: _PyFunction_Vectorcall (call.c:342)
==36158== by 0x4B23B15: UnknownInlinedFun (abstract.h:114)
==36158== by 0x4B23B15: UnknownInlinedFun (abstract.h:123)
==36158== by 0x4B23B15: UnknownInlinedFun (ceval.c:5891)
==36158== by 0x4B23B15: _PyEval_EvalFrameDefault (ceval.c:4213)
==36158== by 0x4B34958: UnknownInlinedFun (pycore_ceval.h:46)
==36158== by 0x4B34958: UnknownInlinedFun (ceval.c:5065)
==36158== by 0x4B34958: _PyFunction_Vectorcall (call.c:342)
==36158==
==36158== 152 bytes in 1 blocks are definitely lost in loss record 431 of 563
==36158== at 0x4842003: operator new(unsigned long) (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==36158== by 0x201A66: pybind11::detail::generic_type::initialize(pybind11::detail::type_record const&) (pybind11.h:1304)
==36158== by 0x32A147: UnknownInlinedFun (pybind11.h:1536)
==36158== by 0x32A147: pybind11::enum_<nextpnr_gowin::PlaceStrength>::enum_<>(pybind11::handle const&, char const*) [clone .constprop.0] (pybind11.h:2150)
==36158== by 0x20346B: nextpnr_gowin::pybind11_init_nextpnrpy_gowin(pybind11::module_&) (pybindings.cc:135)
==36158== by 0x20601F: UnknownInlinedFun (pybindings.cc:88)
==36158== by 0x20601F: pybind11_init_impl_nextpnrpy_gowin (pybindings.cc:88)
==36158== by 0x4BD0FF5: create_builtin (import.c:1012)
==36158== by 0x4BD1CD5: _imp_create_builtin (import.c:1063)
==36158== by 0x4B33D75: cfunction_vectorcall_O (methodobject.c:516)
==36158== by 0x4B297AF: UnknownInlinedFun (ceval.c:5915)
==36158== by 0x4B297AF: _PyEval_EvalFrameDefault (ceval.c:4277)
==36158== by 0x4B34958: UnknownInlinedFun (pycore_ceval.h:46)
==36158== by 0x4B34958: UnknownInlinedFun (ceval.c:5065)
==36158== by 0x4B34958: _PyFunction_Vectorcall (call.c:342)
==36158== by 0x4B23B15: UnknownInlinedFun (abstract.h:114)
==36158== by 0x4B23B15: UnknownInlinedFun (abstract.h:123)
==36158== by 0x4B23B15: UnknownInlinedFun (ceval.c:5891)
==36158== by 0x4B23B15: _PyEval_EvalFrameDefault (ceval.c:4213)
==36158== by 0x4B34958: UnknownInlinedFun (pycore_ceval.h:46)
==36158== by 0x4B34958: UnknownInlinedFun (ceval.c:5065)
==36158== by 0x4B34958: _PyFunction_Vectorcall (call.c:342)
==36158==
==36158== LEAK SUMMARY:
==36158== definitely lost: 616 bytes in 5 blocks
==36158== indirectly lost: 0 bytes in 0 blocks
==36158== possibly lost: 0 bytes in 0 blocks
==36158== still reachable: 140,829 bytes in 585 blocks
==36158== suppressed: 0 bytes in 0 blocks
==36158== Reachable blocks (those to which a pointer was found) are not shown.
==36158== To see them, rerun with: --leak-check=full --show-leak-kinds=all
==36158==
==36158== For lists of detected and suppressed errors, rerun with: -s
Hello,
It seems that the DFF primers do not support clock enable(CE), as of the code.
dffmap = {
"DFF": None,
"DFFN": None,
"DFFS": "SET",
"DFFR": "RESET",
"DFFP": "PRESET",
"DFFC": "CLEAR",
"DFFNS": "SET",
"DFFNR": "RESET",
"DFFNP": "PRESET",
"DFFNC": "CLEAR",
}
apicula/apycula/tiled_fuzzer.py
Line 143 in 4e8e720
The vendor datasheet documented that these DFF with E extension are supported by hardware.
So it there any reason CE is not supported?
PS: latest Yosys seems also support CE.
Is there any way to replace initialisation data for BSRAM in gw1nr devices like you can on ice40 with icebram?
Hello Everyone,
Firstly, I would like to congratulate the devs for the hard work done to reverse engineer gowin chips architectures to make a free EDA tool.
Secondly, I took the blinky.v project to generate pnr file with yosys and nextpnr-gowin with the following files:
blinky.v:
module top (
input clk,
output [`LEDS_NR-1:0] led
);
reg [25:0] ctr_q;
wire [25:0] ctr_d;
// Sequential code (flip-flop)
always @(posedge clk)
ctr_q <= ctr_d;
// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assign led = ctr_q[25:25-(`LEDS_NR - 1)];
endmodule
tangnano4k.cst:
// these are the HDMI pins!
IO_LOC "led[0]" 27;
IO_LOC "led[1]" 28;
IO_LOC "led[2]" 29;
IO_LOC "led[3]" 30;
IO_LOC "led[4]" 31;
IO_LOC "led[5]" 32;
IO_LOC "key" 15;
IO_LOC "rst" 14;
IO_LOC "clk" 45;
CLOCK_LOC "led[0]" BUFS;
CLOCK_LOC "led[1]" BUFS;
CLOCK_LOC "led[2]" BUFS;
CLOCK_LOC "led[3]" BUFS;
CLOCK_LOC "led[4]" BUFS;
CLOCK_LOC "led[5]" BUFS;
// true LVDS pins
IO_LOC "tlvds_p" 35,34;
and, as I said before, then I used yosys and nextpnr-gowin to generate output.json file to future pack it in an .fs file with the following bash commands:
yosys -D LEDS_NR=6 -D OSC_TYPE_OSCZ -p "read_verilog blinky.v; synth_gowin; write_json blinky.json"
nextpnr-gowin --json blinky.json \
--write pnrblinky.json \
--device GW1NSR-LV4CQN48PC7/I6 \
--cst tangnano4k.cst
Then I have got the following error:
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2019 Clifford Wolf <[email protected]> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9 (git sha1 1979e0b)
-- Running command `read -define LEDS_NR=6 OSC_TYPE_OSCZ' --
-- Running command `read_verilog blinky.v; synth_gowin; write_json blinky.json' --
1. Executing Verilog-2005 frontend: blinky.v
Parsing Verilog input from `blinky.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.
2. Executing SYNTH_GOWIN pass.
2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/cells_sim.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT1'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\LUT3'.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\DFF'.
Generating RTLIL representation for module `\DFFN'.
Generating RTLIL representation for module `\DFFR'.
Generating RTLIL representation for module `\VCC'.
Generating RTLIL representation for module `\GND'.
Generating RTLIL representation for module `\IBUF'.
Generating RTLIL representation for module `\OBUF'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\ALU'.
Generating RTLIL representation for module `\RAM16S4'.
Generating RTLIL representation for module `\SDP'.
Successfully finished Verilog frontend.
2.2. Executing HIERARCHY pass (managing design hierarchy).
2.2.1. Finding top of design hierarchy..
root of 0 design levels: top
Automatically selected top as design top module.
2.2.2. Analyzing design hierarchy..
Top module: \top
2.2.3. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
2.3. Executing PROC pass (convert processes to netlists).
2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3.3. Executing PROC_INIT pass (extract init attributes).
2.3.4. Executing PROC_ARST pass (detect async resets in processes).
2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top.$proc$blinky.v:10$1'.
1/1: $0\ctr_q[25:0]
2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches).
2.3.7. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\top.\ctr_q' using process `\top.$proc$blinky.v:10$1'.
created $dff cell `$procdff$3' with positive edge clock.
2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$proc$blinky.v:10$1'.
Cleaned up 0 empty switches.
2.4. Executing FLATTEN pass (flatten design).
No more expansions possible.
2.5. Executing TRIBUF pass.
2.6. Executing DEMINOUT pass (demote inout ports to input or output).
2.7. Executing SYNTH pass.
2.7.1. Executing PROC pass (convert processes to netlists).
2.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.7.1.3. Executing PROC_INIT pass (extract init attributes).
2.7.1.4. Executing PROC_ARST pass (detect async resets in processes).
2.7.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
2.7.1.6. Executing PROC_DLATCH pass (convert process syncs to latches).
2.7.1.7. Executing PROC_DFF pass (convert process syncs to FFs).
2.7.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.7.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>
2.7.4. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
2.7.5. Executing OPT pass (performing simple optimizations).
2.7.5.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.7.5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.5.6. Executing OPT_RMDFF pass (remove dff with constant values).
2.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.5.9. Finished OPT passes. (There is nothing left to do.)
2.7.6. Executing WREDUCE pass (reducing word size of cells).
2.7.7. Executing PEEPOPT pass (run peephole optimizers).
2.7.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.9. Executing TECHMAP pass (map to technology primitives).
2.7.9.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
2.7.9.2. Continuing TECHMAP pass.
No more expansions possible.
2.7.10. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
creating $macc model for $add$blinky.v:14$2 ($add).
creating $alu model for $macc $add$blinky.v:14$2.
creating $alu cell for $add$blinky.v:14$2: $auto$alumacc.cc:474:replace_alu$4
created 1 $alu and 0 $macc cells.
2.7.11. Executing SHARE pass (SAT-based resource sharing).
2.7.12. Executing OPT pass (performing simple optimizations).
2.7.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.7.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.7.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.12.6. Executing OPT_RMDFF pass (remove dff with constant values).
2.7.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.12.9. Finished OPT passes. (There is nothing left to do.)
2.7.13. Executing FSM pass (extract and optimize FSM).
2.7.13.1. Executing FSM_DETECT pass (finding FSMs in design).
2.7.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
2.7.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
2.7.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
2.7.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
2.7.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
2.7.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
2.7.14. Executing OPT pass (performing simple optimizations).
2.7.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.7.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.7.14.3. Executing OPT_RMDFF pass (remove dff with constant values).
2.7.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.14.5. Finished fast OPT passes.
2.7.15. Executing MEMORY pass.
2.7.15.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
2.7.15.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.15.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
2.7.15.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7.15.5. Executing MEMORY_COLLECT pass (generating $mem cells).
2.7.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
2.9. Executing TECHMAP pass (map to technology primitives).
2.9.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/brams_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__GW1NR_SDP'.
Successfully finished Verilog frontend.
2.9.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/cells_sim.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT1'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\LUT3'.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\DFF'.
Generating RTLIL representation for module `\DFFN'.
Generating RTLIL representation for module `\DFFR'.
Generating RTLIL representation for module `\VCC'.
Generating RTLIL representation for module `\GND'.
Generating RTLIL representation for module `\IBUF'.
Generating RTLIL representation for module `\OBUF'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\ALU'.
Generating RTLIL representation for module `\RAM16S4'.
Generating RTLIL representation for module `\SDP'.
Successfully finished Verilog frontend.
2.9.3. Continuing TECHMAP pass.
No more expansions possible.
2.10. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
2.11. Executing TECHMAP pass (map to technology primitives).
2.11.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/drams_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/drams_map.v' to AST representation.
Generating RTLIL representation for module `\$__GW1NR_RAM16S4'.
Successfully finished Verilog frontend.
2.11.2. Continuing TECHMAP pass.
No more expansions possible.
2.12. Executing DETERMINE_INIT pass (determine init value for cells).
2.13. Updated 0 cells with determined init value.
2.14. Executing OPT pass (performing simple optimizations).
2.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.14.3. Executing OPT_RMDFF pass (remove dff with constant values).
2.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.14.5. Finished fast OPT passes.
2.15. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
2.16. Executing OPT pass (performing simple optimizations).
2.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.16.6. Executing OPT_RMDFF pass (remove dff with constant values).
2.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.16.9. Finished OPT passes. (There is nothing left to do.)
2.17. Executing TECHMAP pass (map to technology primitives).
2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
2.17.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/arith_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_gw1n_alu'.
Successfully finished Verilog frontend.
2.17.3. Continuing TECHMAP pass.
Using template $paramod\_80_gw1n_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=26\Y_WIDTH=26 for cells of type $alu.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $pos.
No more expansions possible.
<suppressed ~21 debug messages>
2.18. Executing TECHMAP pass (map to technology primitives).
2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
2.18.2. Continuing TECHMAP pass.
No more expansions possible.
2.19. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).
2.20. Executing dff2dffs pass (merge synchronous set/reset into FF cells).
Merging set/reset $_MUX_ cells into DFFs in top.
2.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 26 unused cells and 14 unused wires.
<suppressed ~27 debug messages>
2.22. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
Selected cell types for direct conversion:
$__DFFS_PP1_ -> $__DFFSE_PP1
$__DFFS_PP0_ -> $__DFFSE_PP0
$__DFFS_PN1_ -> $__DFFSE_PN1
$__DFFS_PN0_ -> $__DFFSE_PN0
$__DFFS_NP1_ -> $__DFFSE_NP1
$__DFFS_NP0_ -> $__DFFSE_NP0
$__DFFS_NN1_ -> $__DFFSE_NN1
$__DFFS_NN0_ -> $__DFFSE_NN0
$_DFF_PP1_ -> $__DFFE_PP1
$_DFF_PP0_ -> $__DFFE_PP0
$_DFF_PN1_ -> $__DFFE_PN1
$_DFF_PN0_ -> $__DFFE_PN0
$_DFF_NP1_ -> $__DFFE_NP1
$_DFF_NP0_ -> $__DFFE_NP0
$_DFF_NN1_ -> $__DFFE_NN1
$_DFF_NN0_ -> $__DFFE_NN0
$_DFF_N_ -> $_DFFE_NP_
$_DFF_P_ -> $_DFFE_PP_
Transforming FF to FF+Enable cells in module top:
2.23. Executing TECHMAP pass (map to technology primitives).
2.23.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/cells_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$__DFFS_PN0_'.
Generating RTLIL representation for module `\$__DFFS_PP0_'.
Generating RTLIL representation for module `\$__DFFS_PP1_'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
2.23.2. Continuing TECHMAP pass.
Using template \$_DFF_P_ for cells of type $_DFF_P_.
No more expansions possible.
<suppressed ~26 debug messages>
2.24. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~26 debug messages>
2.25. Executing SIMPLEMAP pass (map simple cells to gate primitives).
2.26. Executing ABC pass (technology mapping using ABC).
2.26.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 26 gates and 52 wires to a netlist network with 26 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
Removed 0 unused cells and 80 unused wires.
2.27. Executing TECHMAP pass (map to technology primitives).
2.27.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/cells_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$__DFFS_PN0_'.
Generating RTLIL representation for module `\$__DFFS_PP0_'.
Generating RTLIL representation for module `\$__DFFS_PP1_'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
2.27.2. Continuing TECHMAP pass.
No more expansions possible.
2.28. Executing HILOMAP pass (mapping to constant drivers).
2.29. Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).
Mapping port top.clk using IBUF.
Mapping port top.led using OBUF.
2.30. Executing DFFINIT pass (set INIT param on FF cells).
Setting top.$auto$simplemap.cc:420:simplemap_dff$100.INIT (port=Q, net=\ctr_q [19]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$101.INIT (port=Q, net=\ctr_q [20]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$102.INIT (port=Q, net=\ctr_q [21]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$103.INIT (port=Q, net=\ctr_q [22]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$104.INIT (port=Q, net=\ctr_q [23]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$105.INIT (port=Q, net=\ctr_q [24]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$106.INIT (port=Q, net=\ctr_q [25]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$81.INIT (port=Q, net=\ctr_q [0]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$82.INIT (port=Q, net=\ctr_q [1]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$83.INIT (port=Q, net=\ctr_q [2]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$84.INIT (port=Q, net=\ctr_q [3]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$85.INIT (port=Q, net=\ctr_q [4]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$86.INIT (port=Q, net=\ctr_q [5]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$87.INIT (port=Q, net=\ctr_q [6]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$88.INIT (port=Q, net=\ctr_q [7]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$89.INIT (port=Q, net=\ctr_q [8]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$90.INIT (port=Q, net=\ctr_q [9]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$91.INIT (port=Q, net=\ctr_q [10]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$92.INIT (port=Q, net=\ctr_q [11]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$93.INIT (port=Q, net=\ctr_q [12]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$94.INIT (port=Q, net=\ctr_q [13]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$95.INIT (port=Q, net=\ctr_q [14]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$96.INIT (port=Q, net=\ctr_q [15]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$97.INIT (port=Q, net=\ctr_q [16]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$98.INIT (port=Q, net=\ctr_q [17]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$99.INIT (port=Q, net=\ctr_q [18]) to 1'0.
Removed 1 unused cells and 2 unused wires.
2.31. Executing HIERARCHY pass (managing design hierarchy).
2.31.1. Analyzing design hierarchy..
Top module: \top
2.31.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
2.32. Printing statistics.
=== top ===
Number of wires: 60
Number of wire bits: 165
Number of public wires: 4
Number of public wire bits: 59
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 112
ALU 26
DFF 26
GND 52
IBUF 1
OBUF 6
VCC 1
2.33. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
3. Executing JSON backend.
End of script. Logfile hash: da4e88e879
CPU: user 0.10s system 0.00s, MEM: 17.35 MB total, 11.48 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 32% 13x read_verilog (0 sec), 17% 1x share (0 sec), ...
WARNING: CPU random generator seem to be failing, disabling hardware random number generation
WARNING: RDRND generated: 0xffffffff 0xffffffff 0xffffffff 0xffffffff
Info: Series:GW1NS-4 Device:GW1NSR-4C Package:QFN48P Speed:C7/I6
Info: Cell key not found
Info: Cell rst not found
Info: Cell tlvds_p not found
Info: Packing constants..
Info: Packing GSR..
Info: Packing IOs..
Info: Packing diff IOs..
Info: Packing IO logic..
Info: Packing wide LUTs..
Info: Packing LUT5s..
Info: Packing LUT6s..
Info: Packing LUT7s..
Info: Packing LUT8s..
Info: Packing ALUs..
Info: Packing LUT-FFs..
Info: Packing non-LUT FFs..
Info: Checksum: 0xa86b5e2b
Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0xa86b5e2b
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$88_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$89_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$90_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$91_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$92_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$93_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$94_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$87_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$95_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$99_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$97_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$98_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$96_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$100_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$102_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$101_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$85_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$104_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$105_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$106_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$81_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$82_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$83_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$84_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$103_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$86_DFFLC'
ERROR: INTERNAL CHECK FAILED: please report this error with the design and full log output. Failure details are above this message.
0 warnings, 27 errors
As you can see, I am in trouble with the net definitions, the .cst file from tangnano4k I took from the example folder from this repository, the same as blinky.v file.
Can someone tell me what is wrong to make me generate the correct output.json file in order to pack it in an .fs file to flash my tangnano4k?
nextpnr-gowin version:
$ nextpnr-gowin --version
WARNING: CPU random generator seem to be failing, disabling hardware random number generation
WARNING: RDRND generated: 0xffffffff 0xffffffff 0xffffffff 0xffffffff
nextpnr-gowin -- Next Generation Place and Route (Version nextpnr-0.3-37-g8d063d38)
yosys version:
$ yosys -V
Yosys 0.9 (git sha1 1979e0b)
Thanks in advance!!
What is difference between Apycula and Apicula?
Just taking a first look at this project and it is rather confusing. Can you please explain this in README?
I guess aPYcula is pun indicating that tools are made for python. But are there some other non-python components of apicula that i have to install separately in adition to doing pip install apycula
?
DEVICE='GW1N-LV1QN48C6/I5'
BOARD='tangnano'
yosys -D LEDS_NR=3 -p "read_verilog blinky.v; synth_gowin -json blinky.json"
nextpnr-gowin --json blinky.json
--write pnrblinky.json
--device $DEVICE
--cst $BOARD.cst
gowin_pack -d $DEVICE -o pack.fs pnrblinky.json
When I run the example with device GW1N-LV1QN48C6/I5 I get this error:
root@DESKTOP-NSB1HR8:/mnt/d/git/apicula/examples# gowin_pack -d $DEVICE -o pack.fs pnrblinky.json Traceback (most recent call last): File "/root/.venv/python3.10/bin/gowin_pack", line 8, in <module> sys.exit(main()) File "/root/.venv/python3.10/lib/python3.10/site-packages/apycula/gowin_pack.py", line 366, in main with importlib.resources.open_binary("apycula", f"{device}.pickle") as f: File "/usr/lib/python3.10/importlib/resources.py", line 46, in open_binary return reader.open_resource(resource) File "/usr/lib/python3.10/importlib/abc.py", line 433, in open_resource return self.files().joinpath(resource).open('rb') File "/usr/lib/python3.10/pathlib.py", line 1117, in open return self._accessor.open(self, mode, buffering, encoding, errors, FileNotFoundError: [Errno 2] No such file or directory: '/root/.venv/python3.10/lib/python3.10/site-packages/apycula/GW1NNone-1.pickle'
Is it possible to set dual-purpose pins using these tools?
RECONFIG_N and DONE pins need to be set to dual purpose to use UART to CH552 on the Tang Nano.
Configuring dual-purpose pins/pin multiplexing in the Gowin IDE is described here.
Here is the project I am trying to get working on this https://github.com/Eriosies/Tangnano-ASCII2Morse
yosys -D LEDS_NR=6 -p "read_verilog blinky.v; synth_gowin -json blinky.json"
nextpnr-gowin --json blinky.json
--write pnrblinky.json
--device GW1NR-LV9QN88PC6/I5
--cst tangnano9k.cst
gowin_pack -d GW1NR-LV9QN88PC6/I5 -o pack.fs pnrblinky.json
openFPGALoader -b tangnano9k pack.fs
ERROR:
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Parse file Parse pack.fs:
Done
DONE
Error: Failed to claim FPGA device: mismatch between target's idcode and bitstream idcode
bitstream has 0x1100581B hardware requires 0x0100481b
Is it a bug or did i something wrong? i use OSS CAD Suite
Great to find this project,
especially as you are maintaining regularly!!
Have been using IceStorm,
thinking about TangNano.
Do you know of a good guide to understanding FPGA (de)construction?
not verilog, but the mechanics, ie like icestorm;
Seems you might be the person to write one?
as you already understand something of this...
cf. http://pepijndevos.nl/ Contents page please
Comparison of UpDuino/TangNano might help better understanding?
did not find email details
apologies [email protected]
I'm a newbie to the project. I have a Tang-nano1k board and trying to flash a basic led=button project. But when I am using makefile which i wrote using example makefile i got this error:
" ERROR: Incorrect chipdb version 1 is used. Version 2 is required "
I think device name should be different. I am using GW1NZ-LV1QN48C6/I5
my makefile line:
"
any ideas how can i fix it ?
For each model. Like this.
Hi,
Have you tested openFPGALoader for SRAM configuration of bitstream ?
It's seem's to be compatible with Gowin FPGA.
I've been trying to build my_hdmi_device by splinedrive with apicula and have gotten pretty far along with some tweaks.
gowin_pack with the current apicula/chipdb fails with these 2 key errors on the nano4k
gowin_pack -d GW1NS-4 -o chip_balls.fs chip_balls_pnr.json
Traceback (most recent call last):
File "/Users/martell/dev/oss-cad-suite/lib/python3.8/site-packages/Apycula-0.6.2-py3.8.egg/apycula/gowin_pack.py", line 435, in place
File "/Users/martell/dev/oss-cad-suite/lib/python3.8/site-packages/Apycula-0.6.2-py3.8.egg/apycula/chipdb.py", line 941, in loc2bank
KeyError: 'IOB15B'
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
File "/Users/martell/dev/oss-cad-suite/libexec/gowin_pack", line 33, in <module>
sys.exit(load_entry_point('Apycula==0.6.2', 'console_scripts', 'gowin_pack')())
File "/Users/martell/dev/oss-cad-suite/lib/python3.8/site-packages/Apycula-0.6.2-py3.8.egg/apycula/gowin_pack.py", line 703, in main
File "/Users/martell/dev/oss-cad-suite/lib/python3.8/site-packages/Apycula-0.6.2-py3.8.egg/apycula/gowin_pack.py", line 439, in place
Exception: IOB15A is not allowed for a given package
make: *** [chip_balls.fs] Error 1
Steps to reproduce
git clone https://github.com/martell/my_hdmi_device
cd my_hdmi_device
git checkout yosys-nano4k
make -f Makefile.nano4k
@yrabbit @pepijndevos This seems very close since merging #154
I've just started playing with Yosys/nextpnr on a Tang Nano 9K and encountered an issue which I couldn't explain. And I'm unsure if I did something wrong or this is a bug or current limitation of the open source toolchain. The same design works as expected when synthesized with the vendor tools.
The minimized example which triggers the issue is simply turning on an LED when the corresponding button is pressed. Both the LEDs and buttons are active low on the Tang Nano 9K. The only difference between led1
and led2
is that the internal state is inverted.
With the vendor tools led1
and led2
are off after the bitstream is loaded and can be turned on with their corresponding button. But with the open source toolchain led1
is already turned on after the bitstream is loaded, without any button presses. led2
works as expected.
I did also run a post synthesis simulation and both buttons worked as expected in the simulation.
module top (
input clk,
input button1,
input button2,
output [5:0] leds
);
reg led1 = 1'b0;
reg led2 = 1'b1;
always @(posedge clk) begin
if (button1 == 1'b0)
led1 <= 1'b1;
if (button2 == 1'b0)
led2 <= 1'b0;
end
assign leds = { led2, button2, 2'b11, button1, !led1 };
endmodule
IO_LOC "leds[5]" 16;
IO_LOC "leds[4]" 15;
IO_LOC "leds[3]" 14;
IO_LOC "leds[2]" 13;
IO_LOC "leds[1]" 11;
IO_LOC "leds[0]" 10;
IO_LOC "button1" 4;
IO_LOC "button2" 3;
IO_LOC "clk" 52;
yosys -p "read_verilog top.v; synth_gowin -json top.json"
nextpnr-gowin --family GW1N-9C --device "GW1NR-LV9QN88PC6/I5" --cst top.cst --json top.json --write top_pnr.json
gowin_pack --device GW1N-9C -o top.fs top_pnr.json
openFPGALoader top.fs
oss-cad-suite-linux-x64-20230422
There is no documentation on what is in the timing file that was recently decoded.
The readme is also out of date about some recent work.
I also need to add the IRC channel, and eventually Patreon link.
Anything else?
Hello,
I just try with yosys and nextpnr-gowin flow for the blinky example
yosys -p "synth_gowin; write_json blinky.json; show -format svg -prefix aaa;" -f verilog -q blinky.v
nextpnr-gowin --json blinky.json --write pnrblinky.json --device GW1NR-UV9QN881C6/I5 --cst tec0117.cst
Error information of nextpnr-gowin command, is there anything wrong.
Warning: Invalid constraint:
Warning: Invalid constraint: IO_LOC "clk" 35;
Warning: Invalid constraint: IO_LOC "rst" 77;
Warning: Invalid constraint: IO_LOC "led[0]" 86;
Warning: Invalid constraint: IO_LOC "led[1]" 85;
Warning: Invalid constraint: IO_LOC "led[2]" 84;
Warning: Invalid constraint: IO_LOC "led[3]" 83;
Warning: Invalid constraint: IO_LOC "led[4]" 82;
Warning: Invalid constraint: IO_LOC "led[5]" 81;
Warning: Invalid constraint: IO_LOC "led[6]" 80;
Info: Packing constants..
Info: Packing IOs..
Info: Packing LUT-FFs..
Info: Packing non-LUT FFs..
Info: Checksum: 0xe0932f19
Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0xe0932f19
Info: Device utilisation:
Info: SLICE: 28/ 8640 0%
Info: IOB: 9/ 274 3%
Info: Placed 1 cells based on constraints.
ERROR: Unable to place cell '$auto$alumacc.cc:474:replace_alu$4.slice[9].alu', no BELs remaining to implement cell type 'ALU'
10 warnings, 1 error
PS: the example in readme is promote errors with latest yosys repo, so I changed -json to write_json
yosys -p "synth_gowin -json blinky.json" blinky.v
I get a "ValueError: Unknown type at 0x2110d2" when running tiled_fuzzer.py. I have version 1.9.2.02 of the GOWIN IDE installed.
The output for DEVICE=GW1NR-9 is.
Traceback (most recent call last):
File "tiled_fuzzer.py", line 237, in <module>
fse = fuse_h4x.readFse(f)
File "/home/derek/apicula/fuse_h4x.py", line 15, in readFse
tiles['header'] = readOneFile(f, ttyp)
File "/home/derek/apicula/fuse_h4x.py", line 72, in readOneFile
raise ValueError("Unknown type at {}".format(hex(f.tell())))
ValueError: Unknown type at 0x2110d2
DEVICE=GW1N-1 is similar
Traceback (most recent call last):
File "tiled_fuzzer.py", line 237, in <module>
fse = fuse_h4x.readFse(f)
File "/home/derek/apicula/fuse_h4x.py", line 15, in readFse
tiles['header'] = readOneFile(f, ttyp)
File "/home/derek/apicula/fuse_h4x.py", line 72, in readOneFile
raise ValueError("Unknown type at {}".format(hex(f.tell())))
ValueError: Unknown type at 0x162792
I am trying to compile nextpnr-gowin after installing apycula using this github action:
https://github.com/philiprbrenan/nextPnr/actions/runs/5565472535/jobs/10165851576
The compilation process terminates with the following message concerning an apycula file:
FileNotFoundError: [Errno 2] No such file or directory: '/usr/local/lib/python3.10/dist-packages/apycula/GW2A-18.pickle'
Please tell me how to obtain this file?
I leave it here so I don't forget it.
Sometimes the generated image cannot be flashed with openFPGALoader --- it complains about missing IDCODE.
I haven't looked into it yet, but attached two versions of both the original .JSON and the resulting .FS
rabbit@fly ~/src/apicula/examples% diff -u ~/tmp/bad/shift-tangnano-bad.fs ~/tmp/good/shift-tangnano-good.fs|head
--- /home/rabbit/tmp/bad/shift-tangnano-bad.fs 2021-11-29 10:51:19.089890000 +1000
+++ /home/rabbit/tmp/good/shift-tangnano-good.fs 2021-11-29 10:49:28.988690000 +1000
@@ -1,4 +1,4 @@
-1011101111100001
+1110100010101110
1111111111111111
This is more as a place to store interesting files related to the problem than issue.
So I took shift.v and got shift-tangnano4k-synth.json
:
shift-tangnano4k-synth.json.zip
Then I made a .CST file that fixed all cells, not just IO.
shift-7.cst.zip
Then using the same synth.json
and .cst
file I generated many, many pnr.json
files with different seed values until I got two images: a working one and a faulty one.
Next I compared the two `pnr.json'. The only difference was the routing. Ok, there is one LUT which is different, but I think this is not critical since this is the source of the VCC.
diff.txt
shift-7-1.json.zip
shift-7-2.json.zip
for some reason the code uploaded to the device will disappear the moment that the device is powered down. is that supposed to happen? how do i make it not do that?
hi, gowin fpga seems not open source, why you guys so powerful to generate the bitstream file? How can you do that? thanks
I think my python installation is wrong but can found why. With python3.7 (virtualenv) I have this exception in fuzzer step :
$ python tiled_fuzzer.py # makes $DEVICE.pickle
Traceback (most recent call last):
File "tiled_fuzzer.py", line 17, in <module>
import pindef
File "/home/fabien/myapp/apicula/pindef.py", line 1, in <module>
import pandas as pd
File
"/home/fabien/pyenv/pyenv37/lib/python3.7/site-packages/pandas/__init__.py",
line 54, in <module>
from pandas.core.api import (
File
"/home/fabien/pyenv/pyenv37/lib/python3.7/site-packages/pandas/core/api.py",
line 29, in <module>
from pandas.core.groupby import Grouper, NamedAgg
File
"/home/fabien/pyenv/pyenv37/lib/python3.7/site-packages/pandas/core/groupby/__init__.py",
line 1, in <module>
from pandas.core.groupby.generic import DataFrameGroupBy, NamedAgg,
SeriesGroupBy
File
"/home/fabien/pyenv/pyenv37/lib/python3.7/site-packages/pandas/core/groupby/generic.py",
line 60, in <module>
from pandas.core.frame import DataFrame
File
"/home/fabien/pyenv/pyenv37/lib/python3.7/site-packages/pandas/core/frame.py",
line 104, in <module>
from pandas.core.generic import NDFrame, _shared_docs
File
"/home/fabien/pyenv/pyenv37/lib/python3.7/site-packages/pandas/core/generic.py",
line 99, in <module>
from pandas.io.formats import format as fmt
File
"/home/fabien/pyenv/pyenv37/lib/python3.7/site-packages/pandas/io/formats/format.py",
line 75, in <module>
from pandas.io.common import stringify_path
File
"/home/fabien/pyenv/pyenv37/lib/python3.7/site-packages/pandas/io/common.py",
line 3, in <module>
import bz2
File "/usr/local/lib/python3.7/bz2.py", line 19, in <module>
from _bz2 import BZ2Compressor, BZ2Decompressor
ModuleNotFoundError: No module named '_bz2'
I installed the packet libbz2-dev but with the same error.
$ sudo apt-get install libbz2-dev
I had to install the data classes python module to run dat19_h4x.py.
When following the quick start up instructions for the sipeed tang nano, when running nr$ bash simple.sh blinkygw1n1.v # Tang Nano
It returns (at the end):
Info: Routing..
Info: Setting up routing queue.
ERROR: Found two arcs with same sink wire R11C10_A0: ctr[23] (3) vs ctr[24] (2)
ERROR: Routing design failed.
0 warnings, 2 errors
Note I tried the previous steps with several available version of gowin IDE, and I got the same output with the other example
best regards,
Paulo
I followed the tutorial given in main README for the board TEC0117.
$ export GOWINHOME=/chemin/de/linstallation/gowin/IDE/
$ export DEVICE="GW1NR-9" # TEC0117
$ python dat19_h4x.py # makes $DEVICE.json
$ python tiled_fuzzer.py # makes $DEVICE.pickle
$ cd generic
$ bash simple.sh blinky.v # TEC0117
$ cd ..
$ python gowin_pack.py generic/pnrblinky.json
$ python gowin_unpack.py pack.fs
$ yosys -p "read_verilog -lib +/gowin/cells_sim.v; clean -purge; show" unpack.v
$ openFPGALoader -m -b littleBee pack.fs # FOSS programmer
The bitstream pack.fs has been generated and downloaded with openFPGALoader but LEDs doesn't blink. All LED are on.
I used official Β«pinoutΒ» from Gowin website maybe it's that ?
I have an error after downloading the bitstream but I read on this issue that is a known bug.
For ice40
chips there is icestorm/icepll, for ecp5
chips there is trellis/ecppll.
I wonder is there any similar tools/examples for gw1n
chips?
Just starting using this toolchain, so I might be using it wrong... Anyway, if this feature has not been implemented yet, I might as well lend a hand :)
blinky.v don't work (tested on 2 boards), but blinky-osc.v works fine.
After adding --enable-gobals works again, but after some unrelated changes in v file broken again
(after rebuild & reflash)
Hello,
Just a question when studying the source code.
def _io_mode_sort_func(mode):
l = len(mode[1].decode_bits) * 10
if mode[0] == 'IOBUF':
l += 2
elif mode[1] == 'OBUF': # is it a typo here? mode[0] possible values are IOBUF,OBUF, but mode[1] is the value of the dict ( type Dict[str, Set[Coord]])
l += 1
return l
apicula/apycula/gowin_unpack.py
Lines 34 to 40 in ec90ea2
I get the following unexpected message when I try to run the --gui version of nextpnr-gowin on Ubuntu 20:
nextpnr-gowin --gui --device "GW1NR-LV9QN88PC6/I5"
Info: Series:GW1N-9 Device:GW1NR-9 Package:QFN88P Speed:C6/I5
terminate called after throwing an instance of 'std::out_of_range'
what(): dict::at()
Aborted (core dumped)
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