Comments (6)
Ok on closer inspection it looks like the hadder module is referenced on line 75 (cellref hadder), but the actual cell is
defined below it.
Looks like the deepest parts of the hierarchy need to be declared at the top.
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Confirmed, if I edit the edif file manually to put the hadder cell above the adder cell, then Xilinx accepts it.
I took a quick look at how the edif backend works, but still trying to work it out. :)
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Awesome, the ripple carry adder works on zedboard :)
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ack. I'll add topological sorting to the edif backend.
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I just pushed commit cd0fe7d which contains topological sorting in edif backed.
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Cheers :)
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Related Issues (20)
- CXXRTL: >20x compile time regression with clang++-18 HOT 3
- Wrongly assign the name internal signal for vhdl HOT 1
- The $check cell could not support TRG_WIDTH > 1 lead to old design verification failed with `async2sync` command. HOT 2
- formal: Produced traces make it look like asserts trigger a clock step too late HOT 7
- Yosys Verilog Parsing Error: Unable to Synthesize After Reading File HOT 2
- cell reference names appear to be truncated
- Ensuring smooth Yosys-to-Synlig compatability and tracking HOT 13
- Clean up uses of #if(n)def EMSCRIPTEN
- Throws a segmentation fault if the 'input.blif' file's size is huge. HOT 2
- Stub RTL Generation Feature
- Performance Issue: Synthesis Takes Too Long to Complete HOT 9
- system verilog "import" command not recognized (ERROR: syntax error, unexpected TOK_ID) HOT 3
- check-git-abc in Makefile for the first compile time HOT 4
- `count_id(cell->name) == 0` failure HOT 1
- IDES4_MEM gowin module is missing HOT 2
- Feature Request: Add Support for Input Filelist Option HOT 8
- CologneChip synthesis fails silently (simulation discrepancies) HOT 2
- Yosys Synthesis Error: Hash Table Exceeded Maximum Size HOT 8
- support error for Aggregate Initialization and Replication HOT 1
- Unable to code FSM into binary format HOT 2
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