Comments (3)
cliffordwolf
commented on August 17, 2024
yes, this is a bug. thanks for the report.
I've put it on my todo list now. but this todo list is growing lately so it might be a week or two until I get to fixing this.
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cliffordwolf
commented on August 17, 2024
This turned out to be much easier to get right than I initially anticipated. It is fixed now: 507c63d
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getvictor
commented on August 17, 2024
I updated Yosys on EDA Playground. The example now works on rerun: http://www.edaplayground.com/s/4/490
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Related Issues (20)
- <<EOT doesn't work from the command line
- Multibit `reg` crashes Yosys without an error HOT 2
- In cxxrtl case item expressions are compared in an unexpected order HOT 3
- `DP16KD` blackbox model is missing at least `CLKAMUX` and `CLKBMUX` ports.
- Write first RAM using blocking assignments synthesized as Read first RAM HOT 1
- CXXRTL output doesn't compile with zero-sized ports on modules HOT 4
- segmentation fault : cmd hierarchy HOT 2
- setparam makes hierarchy fail HOT 3
- Assertion fail with chparam.
- ABC9 "&mfs" step gives incorrect result on big endian for objects with >5 variables HOT 8
- cxxrtl should not be counting steps in `module::step()` HOT 1
- Confusing error message when using default_nettype none and a local is defined in unnamed block in verilog mode
- [Bug] `yosys.exe` doesn't output anything on Windows 10 Pro HOT 1
- Import package error
- Synthesis optimization error, inconsistent simulation results HOT 3
- Yosys: Segmentation Fault while executing ABC HOT 2
- How do I get the AST tree๏ผ HOT 1
- Multiple edge sensitive events found for this signal
- Can't find object for defparam
- Abort in kernel/fmt.cc:454 with "$display($time)" called
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