Related Issues (20)
- Error Arises During Synthesis due to Verilog Code Structure HOT 3
- Use /usr/bin/env for bash on remaining places
- synth_nexus with -abc9: CCU2 cells get the low order CIN connected to constant 1'b0 HOT 2
- crash in select and delete HOT 1
- `sim` doesn't consider assertions failed if EN=x A=0 HOT 1
- Can't call DPI function with no return (void return type) HOT 2
- Gowin BSRAM inference -- We need B suffix (such as DPB instead of current DP) HOT 52
- Segmentation fault with verific HOT 2
- Defect in btor2 file format generation
- ERROR: Unsupported internal cell `$pow' HOT 3
- Bug with modulo in CXXRTL when operands intersect HOT 5
- Bug: Logic and arithmetic left shifts sometimes overflow the output signal HOT 8
- Bug: incorrect division in CXXRTL HOT 4
- Bug: Shifts (in both directions) consider the operand signed under some conditions in CXXRTL
- Bug: Segmentation fault during step for CXXRTL HOT 6
- `read_blif; write_blif; read_blif;` doesn't work HOT 3
- Performance issue with many concatenations in CXXRTL HOT 2
- Add a generic way to delete all non-synthesizable cells HOT 2
- Share pass uses too much system memory for large combinatorial networks HOT 2
- Tech lib DSP_A/B_MINWIDTH value change causes ABC9 error
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