Comments (2)
You have line breaks between the file names, which is an error: line break starts a new command. (The semicolons in your script are useless since they are not separating two commands on the same line.)
I can't reproduce a segfault, I get an error as expected: ERROR: Reading Verilog/SystemVerilog sources failed.
If I replace all line breaks with spaces in the script, it seems to work correctly, and I get the error VERIFIC-ERROR [VERI-1517] cannot open Verilog file './sqed-generator/SQED-Generator/QEDFiles/inst_constraints.v'
- and there is indeed no such file.
from yosys.
Run the script ./setup-sqed-generator.sh to install the SQED generator (a git repository will be cloned from GitHub).
Run the script ./generate-qed-files.sh to generate the Verilog sources of the generic QED module for RIDECORE.
Run the script ./wire-up-qed-module.sh to wire up the QED module to the RIDECORE design and apply simplifications to speed up model checking.
from yosys.
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from yosys.