Comments (2)
I’ve seen the same issue. Try it with clang++. It’s orders of magnitude faster on some template based code. And CXXRTL is nothing but templates.
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Yeah, this is basically expected. I think this could be handled by splitting expressions into subexpressions when they reach a maximum depth.
from yosys.
Related Issues (20)
- Abnormal output
- create a pip install package wheel for Windows HOT 3
- Enhancing Syntax Checking for Port Declarations in Yosys HOT 2
- Yosys right shift error HOT 7
- A topological loop is generated after using async2sync HOT 2
- CXXRTL: >20x compile time regression with clang++-18 HOT 3
- Wrongly assign the name internal signal for vhdl HOT 1
- The $check cell could not support TRG_WIDTH > 1 lead to old design verification failed with `async2sync` command. HOT 2
- formal: Produced traces make it look like asserts trigger a clock step too late HOT 7
- Yosys Verilog Parsing Error: Unable to Synthesize After Reading File HOT 2
- cell reference names appear to be truncated
- Ensuring smooth Yosys-to-Synlig compatability and tracking HOT 13
- Clean up uses of #if(n)def EMSCRIPTEN
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- system verilog "import" command not recognized (ERROR: syntax error, unexpected TOK_ID) HOT 3
- check-git-abc in Makefile for the first compile time HOT 4
- `count_id(cell->name) == 0` failure HOT 1
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