Comments (2)
Yes, a cmd line switch to disable this share pass would be great, ex. if -noshare
existed to use in this case.
I would turn that switch on for this particular version of the design to disable share. The goal here is to continue to PnR and evaluate the timing of the large combinatorial path. So this version of code will never see real hardware, just collecting data.
However, given the data collected, the large comb. network is pipelined and that version of the design would benefit from turning share back on (not being all comb. shouldnt use a bunch of ram). That design absolutely runs on ecp5 does very cool stuff in hardware 🤓 https://blog.yosyshq.com/p/3d-raytracing/ <ghdl,yosys,nextpnr3
from yosys.
Yes, this is known/expected given the way share works. Although I didn't expect to need a -noshare
option (like the synth
pass has) for smaller devices, as I thought it's not likely to run into designs that cause excessive time/memory usage, but it seems you managed to find one. Is the design realistic/something you would actually want to run on an ecp5 board in practice, or more of a benchmark?
Either way, the only solution I can think of is not running share for this design.
from yosys.
Related Issues (20)
- Inout port not working with array replication operator HOT 6
- Add support for SystemVerilog's `==?` and `!=?` operators
- Unexpected Result from `synth_gowin` Pass HOT 4
- No bad property in btor2 file generated from verilog (`write_btor` should error for `$check` cells) HOT 3
- Build error: `make: *** [Makefile:810: abc/abc] Error 2` HOT 4
- Documentation is unreadable if the system theme is dark HOT 5
- Wired-or (wor) wires generate $or / $reduce_or cells in output HOT 3
- Nothing of abc folder contents at git clone https://github.com/YosysHQ/yosys.git HOT 1
- Yosys seems to handle bit operations on empty strings inconsistently with the original design. HOT 4
- The negation operation on an empty string results in an exception. HOT 6
- Outputs differ before and after synthesis, but Yosys seems correct.
- read_verilog doesn't respect `signed` keyword HOT 2
- make error 'abc' is not configured as a git submodule. HOT 12
- CXXRTL: Information loss when outputs are aliased HOT 4
- Abnormal output
- create a pip install package wheel for Windows HOT 3
- Enhancing Syntax Checking for Port Declarations in Yosys HOT 2
- Yosys right shift error HOT 7
- A topological loop is generated after using async2sync HOT 2
- CXXRTL: >20x compile time regression with clang++-18 HOT 3
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