Comments (2)
I think the warnings demonstrate that Yosys is absolutely detecting the issues; it's just permissively accepting them.
For this, there is the -e
option to Yosys:
-e regex
if a warning message matches the regex, it is printed as error
message instead and the tool terminates with a nonzero return code.
from yosys.
The read_verilog help explicitly says the following:
Note that the Verilog frontend does a pretty good job of processing valid
verilog input, but has not very good error reporting. It generally is
recommended to use a simulator (for example Icarus Verilog) for checking
the syntax of the code, rather than to rely on read_verilog for that.
I think this is probably a wontfix
situation.
from yosys.
Related Issues (20)
- Inout port not working with array replication operator HOT 6
- Add support for SystemVerilog's `==?` and `!=?` operators
- Unexpected Result from `synth_gowin` Pass HOT 4
- No bad property in btor2 file generated from verilog (`write_btor` should error for `$check` cells) HOT 3
- Build error: `make: *** [Makefile:810: abc/abc] Error 2` HOT 4
- Documentation is unreadable if the system theme is dark HOT 5
- Wired-or (wor) wires generate $or / $reduce_or cells in output HOT 3
- Nothing of abc folder contents at git clone https://github.com/YosysHQ/yosys.git HOT 1
- Yosys seems to handle bit operations on empty strings inconsistently with the original design. HOT 4
- The negation operation on an empty string results in an exception. HOT 6
- Outputs differ before and after synthesis, but Yosys seems correct.
- read_verilog doesn't respect `signed` keyword HOT 2
- make error 'abc' is not configured as a git submodule. HOT 12
- CXXRTL: Information loss when outputs are aliased HOT 4
- Abnormal output
- create a pip install package wheel for Windows HOT 3
- Enhancing Syntax Checking for Port Declarations in Yosys HOT 2
- Yosys right shift error HOT 7
- A topological loop is generated after using async2sync HOT 2
- CXXRTL: >20x compile time regression with clang++-18 HOT 3
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from yosys.