Comments (3)
It is not really doing anything here. The "removing top bits" does not actually remove the bits. It changes the wiring around and lets a later "clean" actually get rid of them. When you call "clean" between two calls to "wreduce" then the loop will stop. When you just call "wreduce" in a loop it will prepare this wires in a way that "clean" can get rid of them over and over again.. (It renames the wires, thus it looks like its a different wire in each iteration.)
I have now fixed this in commit 0748ef6. Now wreduce recognizes the already-prepared-for-deletion wires and does not touch them a second time.
from yosys.
Ah, I understand. Perhaps a note about this could be added to the wreduce documentation/output that it needs to be run in conjunction with clean?
while you're at it there is a typo in the title of this page as well (is->if)
http://www.clifford.at/yosys/cmd_wreduce.html
I am under the impression that you are looking for bug reports/typos etc for even minor things, but if you are not, let me know so you can focus on higher priorities.
from yosys.
Perhaps a note about this could be added to the wreduce documentation
This is a general theme in Yosys, not specific to the wreduce command. (The help message to opt_clean has something on it and I've now added some additional explanations to the CodingReadme file.)
while you're at it there is a typo in the title of this page as well
fixed. (webpage will be updated when I release yosys 0.6)
I am under the impression that you are looking for bug reports/typos etc for even minor things, ...
Yes. A steady flow of easy to fix bug reports is very welcome.. ;)
Let me just add a more detailed explanation of what was going on with wreduce (for the record):
Say you have a signal a[5:0]
and only the lower 4 bits of it are used, so "wreduce" tries to "remove" the top two bits. I cannot remove a Wire object (or make it shorter, see the explanation in CodingReadme I mentioned above). So I instead create a new wire $temp42[3:0]
and essentially add assign $temp42[3:0] = a[3:0]
to the design. Finally I rename $temp42
to a
and a
to $temp42
. The next call to "clean" will remove the wire $temp42
.
Before my bugfix, if you called "wreduce" a 2nd time it looked at the $temp42[5:0]
wire and said "hay - I can remove the two top bits from it", create a $temp43[3:0]
, assign $temp43[3:0] = $temp42[5:0]
and flip the names. Now after the bugfix "wreduce" understands that it is operating on wires that "clean" would throw away anyways and simply skips them.
from yosys.
Related Issues (20)
- Wrongly assign the name internal signal for vhdl HOT 1
- The $check cell could not support TRG_WIDTH > 1 lead to old design verification failed with `async2sync` command. HOT 2
- formal: Produced traces make it look like asserts trigger a clock step too late HOT 7
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- Ensuring smooth Yosys-to-Synlig compatability and tracking HOT 13
- Clean up uses of #if(n)def EMSCRIPTEN
- Throws a segmentation fault if the 'input.blif' file's size is huge. HOT 2
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- Performance Issue: Synthesis Takes Too Long to Complete HOT 9
- system verilog "import" command not recognized (ERROR: syntax error, unexpected TOK_ID) HOT 3
- check-git-abc in Makefile for the first compile time HOT 4
- `count_id(cell->name) == 0` failure HOT 1
- IDES4_MEM gowin module is missing HOT 2
- Feature Request: Add Support for Input Filelist Option HOT 8
- CologneChip synthesis fails silently (simulation discrepancies) HOT 2
- Yosys Synthesis Error: Hash Table Exceeded Maximum Size HOT 8
- support error for Aggregate Initialization and Replication HOT 1
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from yosys.