Failed to detect width for parameter with expression about yosys HOT 3 CLOSED

You can work around that problem by making sure the parameter is defined before it is being used. You can do that by either going all-in with the Verilog-2001 syntax for port and parameter declarations:

module test2 #( 
    parameter WIDTH = 16 * 2
) (
    output [WIDTH-1:0] out
);
endmodule

Or by falling back to the Verilog-95 syntax:

module test3 (out);
    parameter WIDTH = 16 * 2;
    output [WIDTH-1:0] out;
endmodule

I'll see if I can fix this and post another comment then.

Would you consider fixing this bug

I would not call it a bug. E.g. modelsim also refuses to process your code:

-- Compiling module multiply
** Error: test2.v(5): (vlog-2730) Undefined variable: 'A_WIDTH'.
** Error: test2.v(5): 'a' already declared in this scope (multiply).
** Error: test2.v(6): (vlog-2730) Undefined variable: 'B_WIDTH'.
** Error: test2.v(6): 'b' already declared in this scope (multiply).
** Error: test2.v(7): (vlog-2730) Undefined variable: 'OUT_WIDTH'.
** Error: test2.v(8): 'out' already declared in this scope (multiply).
....

And modelsim is even pickier: It doesn't matter if the parameter points to an expression or a literal. The only difference is that modelsim creates better error messages.

from yosys.

Fixed in commit 422794c.

from yosys.

Thanks for the quick reply and fix! That's really helpful!

from yosys.