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mnist

Neural Network with single hidden layer learning MNIST with less than 1.2% test error.

neural-networks-on-silicon

This is a collection of works on neural networks and neural accelerators.

opensift

Open-Source SIFT Library

papaa-opencl

OpenCL Labs for PAPAA Summer School 2016 Edition

pbmve

pothoszynq

DMA source and sink blocks for Xilinx Zynq FPGAs

pynq-classification

Python on Zynq FPGA for Convolutional Neural Networks

rigel

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.

rnn.blstm.hls.zynq

Hardware architecture and its implementation of Recurrent Neural Network with Bidirectional Long Short-Term Memory and Connectionist Temporal Classification Layer for Optical Character Recognition

scanline-stereo-vision-fpga

Implementazione VHDL dell’algoritmo Scanline

sift-implementation-in-verilog

Using Verilog to implement the SIFT algorithm into an FPGA for small robotic situations

simplified-deeplearning

Simplified implementations of deep learning related works

slam

learning SLAM,curse,paper and others

slambook

songjhh_blog

通过spring+spring mvc+mybatis+shiro搭建的博客系统

stereocensus

Verilog Implementation of the Census Transform Stereo Vision algorithm

stereovision

A stereo vision core built upon an pixel processing pipeline framework

stereovision-1

Library and utilities for 3d reconstruction from stereo cameras.

svm-gaussian-classification-fpga

SVM Gaussian Classifier of 30x30 greyscale image on Verilog

testkey

Android 按键测试程序 20141024添加蓝牙耳机按键监听

ufldl

The solution of Andrew Unsupervised Feature Learning and Deep Learning

ufldl-tutorial

Deep Learning and Unsupervised Feature Learning Tutorial Solutions

verilog-multilayer-perceptron

HDL implementation of a pipelined multilayer perceptron (neural network)

xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

yulifei.github.io

zedboard-vivado-loopback

Zedboard loopback Vivado project for use with the zynq-xdma driver

znn

Repository for neural network engines for Zynq FPGAs

zynq-soc-training

Zynq SoC Training By EmbeddedCentric.com

zynq-vdma-driver-stereovisionapp

zynqnet

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"