In order to make use of content of this repository you need to:

1. Have ZedBoard Rev. D
2. Have Xilinx SDK installed. (For this version, I worked with with Xilinx SDK 2018.1)
3. You don’t need Vivado, as output from Vivado is committed here.

The design of hardware is documented in zedboard_swsleds_irq.pdf. In a nutshell, the GPIO IP (axi_gpio_0) is configured for a dual-channel mode where channel 1 is connected to the DIP switches and channel 2 is connected to the LEDs. The GPIO IP has interrupts enabled (axi_gpio_0/ip2intc_irpt) and hooked up to ZYNQ (processing_system7_0/IRQ_F2P[0:0]).

After cloning the repository you need to:

1. Start Xilinx SDK, and
2. Import the Eclipse projects with File > Open Projects from File System... from: zedboard_swsleds_irq_hw_platform_0, zedboard-swsleds-irq_bsp, zedboard-swsleds-irq, zedboard-swsleds-freertos_bsp and zedboard-swsleds-freertos directories.

Build the project zedboard-swsleds-irq and/or zedboard-swsleds-freertos with Project > Build Project.

Note 1: As indicated by its name, the project zedboard-swsleds-freertos uses FreeRTOS in order achieve the required functionality.

Note 2: In the project zedboard-swsleds-irq , the source file zedboard-swsleds-irq/src/zedboard-swsleds-irq.c has on in its first line the following #define:

#define IS_IRQ_ON 1

This #define controls operation of the software - for IS_IRQ_ON == 1 the interrupts are enabled, for IS_IRQ_ON == 0 the interrupts are disabled and the LEDs are turned off/on in a polling mode.

1. Program your FPGA with Xilinx > Program FPGA with the pre-built image zedboard_swsleds_irq.bit (the blue LED Done should light up).
2. Deploy the resultant zedboard-swsleds-irq.elf or zedboard-swsleds-freertos.elf file built in the Building step to the board with Run As > Launch on Hardware (GDB).
3. You should be able to turn the LEDs on and off with the DIP switches.

One might want to boot their board of the flash memory that is available on ZedBoard. For this purpose I added extra two projects, namely zedboard-swsleds-fsbl_bsp and zedboard-swsleds-fsbl, that allow for creation of a BOOT.mcs file, i.e. the file for booting of the QSPI flash. The procedure for enabling such a boot mode is as follow:

1. Build one of the projects zedboard-swsleds-irq or zedboard-swsleds-freertos (and their dependencies).

2. Build the project zedboard-swsleds-fsbl (and its dependency zedboard-swsleds-fsbl_bsp).

3. Create the boot image by means of Xilinx > Create Boot Image dialog.

4. In this dialog select:
   4.1 Output format: MCS.
   4.2 Boot image partitions: (bootloader) zedboard-swsleds-fsbl.elf, zedboard_swsleds_irq.bit, either zedboard-swsleds-irq.elf or zedboard-swsleds-freertos.elf (in this order).
   4.3 Name your output .mcs file.

   • Once that information is entered, click the Create Image button.

5. Use Xilinx > Program Flash to program the memory with the created image.

6. Make sure that the Boot Mode jumpers are set for booting of the flash (MIO3: 0, MIO4: 0, MIO5: 1) before next powering of the board.