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implementation-of-ofdm-transmitter-using-intel-de2i--150-fpga-board

Using the Quartus II software, a OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the digital modulation technique and Altera FFT MegaCore Function has been used to implement the Inverse Fast Fourier Transform block. The output of the OFDM transmitter is displayed on the monitor by implementing VGA Controller

mangomips32

A softcore microprocessor of MIPS32 architecture.

memory_arbiter_verilog

Request/Grant based Memory Bus Arbiter designed as FSM using Verilog.

midgetv

rv32i/rv32im/rv32imc for iCE40. Wishbone interface.

mips

A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

mips-architecture-cpu-design

BUAA SCSE - Computer Organization - Pipeline CPU design

mips-architecture-cpu-design-based-on-fpga

基于FPGA的MIPS架构的CPU设计

mips-cpu

MIPS CPU implemented in Verilog

mips-cpu-design

用 Verilog 设计实现的简易单周期和多周期 CPU。中山大学计算机组成原理实验（2018 秋）

mips-pipeline-processor

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

mips32-cpu

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

mips48pipelinecpu

冯爱民老师《计算机组成原理A》课程设计

my_design

带有tlb的五级流水CPU

nanodap

由于部分淘宝卖家“借鉴”缪斯实验室出的nanoDAP详情及描述，请大家认准Muse Lab官方店铺

nitro-parts-lib-spi

Verilog SPI master and slave

nncu_tool

NN toolkit for MCU package

npu_on_fpga

在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。

nysa-verilog

Verilog Repository for GIT

odin

ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.

ofdm_ise

ofdm_modem

opene902

OpenXuantie - OpenE902 Core

pd_usb

processor-cache

A Verilog implementation of a processor cache.

qspi_for_soc

QSPI for SoC

reindeer

PulseRain Reindeer - RISCV RV32I[M] Soft CPU

risc-v-32i

体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器

risc-v_article_paper_src

riscv资料、论文等

risc-v_cpu

This is a FPGA supported RISC-V CPU with 5-stage pipeline and 2-way set associative cache implemented in Verilog HDL.

riscv

RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU