1801bm1 / cpu11 Goto Github PK

It was reported the opcode prefetch bug is not completely fixed.

If VM2_CORE_FIX_PREFETCH is nonzero the PC2 prefetch bug fix is applied (not completely works, as it was found).

Original 1801BM2 processor contains microcode bug happening at the following conditions:
- two operands PDP-11 instruction is being executed
- source has addressing method @pc (field value 17 octal)
- destination does not involve PC (dst register field !=7)
- no extra instruction words are used by destination (no E(Rn),@e(Rn))
- Q-bus is slow and opcode prefetch is not completed before microcode
starts source field processing and fetching the source data (slow nRPLY/nAR)

The problem is the failure to update the “frozen” copy registers CPC and CPSW after the MTPS command, when the registers should be “unfrozen” and receive the current values of PC and PSW. The USER mode interrupts themselves are pushed onto the stack not by PC and PSW, but by CPC and CPSW. The FIS service is written in such a way that if it was called with interrupts enabled, then it should be executed in HALT mode with interrupts enabled. It starts in HALT mode with interrupts disabled, first saving all registers, CPC and CPSW. And then with the MTPS R0 command, it sets the same priority that was when calling the FIS command. An interrupt may occur immediately after this command. In the original 1801BM2, CPC and CPSW are immediately “unfrozen” and become equal to the current PC and PSW, respectively, they are already put on the stack. And in the FPGA version, after “defrosting” they do not have time to receive the current values of PC and PSW, and “frozen” values are put on the stack, i.e. PC and PSW after the FIS command.

Test code

000004/ 6
000006/ 0
000010/ 12
000012/ 0

000100/ 104
000102/ 200
000104/ 21627
000106/ 160000
000110/ 103402
000112/ 5237
000114/ 120
000116/ 2

001000/ 106427
001002/ 0
001004/ 5037
001006/ 120
001010/ 12706
001012/ 1000
001014/ 5046
001016/ 5046
001020/ 5046
001022/ 5046
001024/ 75006
001026/ 20627
001030/ 774
001032/ 1766
001034/ 0
001036/ 0

000760/ 0
000762/ 0
000764/ 0
000766/ 0
000770/ 0
000772/ 0
000774/ 0
000776/ 0

R0/ 0
R1/ 0
R2/ 0
R3/ 0
R4/ 0
R5/ 0
R6/ 1000
R7/ 1000

Fail result on FPGA BM2

1000G 001036
120/000002
760/177017
762/177015
764/001026
766/000004
770/000000
772/000000
774/000000
776/000000
R0/000004
R1/000000
R2/173044
R3/000000
R4/000000
R5/000000
R6/000770
R7/001036

000002 in address 000120 says that FIS was successfully interrupted twice after MTPS.
On the stack, address 000764 is 001024 and address 000766 is 4. These are the CPC and CPSW after the FADD SP command at address 001024.

It seems that this also happened when switching to a synchronous processor model.
And simple workaround for fix CPSW:

+always @(posedge vm_clk_n)
-always @(posedge vm_clk_p)
begin
   if (pswt_wa) psw[4] <= ax[4];
   if (psw_wa) psw[7:5] <= ax[7:5];
   if (psw8_wa) psw[8] <= ax[8];
end

+always @(posedge vm_clk_n)
-always @(posedge vm_clk_p)
begin
   if (psw_wa)
      psw[3:0] <= ax[3:0];
   else
   begin
      if (pswc_stb) psw[0] <= cond_c;
      if (psw_stb)  psw[1] <= cond_v;
      if (psw_stb)  psw[2] <= cond_z;
      if (psw_stb)  psw[3] <= cond_n;
   end
end

I think we need to change blocking to non blocking statements.

-       bir_fix = (breg[14:12] != 3'o0)    // two ops instructions
+       bir_fix <= (breg[14:12] != 3'o0)    // two ops instructions

In these places:

When the VIRQ request does not acknowledge the interrupt vector, interrupts should occur at address SEL274, but the usual interrupt 004 occurs. Analysis of the problem showed that the reason is that the pli_ack signal is one clock cycle behind p[6] = acin & qbto & iako.

It seems that this happened when switching to a synchronous processor model. This is not a problem at the DVK and UKNC, but it is critical for the work of the Souyz Neon.
I made a workaround by delaying the end of the wbi_stb_o signal by one clock cycle, but I’m not sure that this is the best solution.

+reg   old_wbi_stb_o;

always @(posedge vm_clk_p)
begin
+  old_wbi_stb_o <= wbi_stb_o;
-   vec_stb <= wbi_stb_o & ~wbi_una_o; 
+  vec_stb <= (wbi_stb_o | (old_wbi_stb_o & ~wbi_stb_o )) & ~wbi_una_o;