Basic Static Timing Analysis concepts, timing library concepts, STA flow, SDC constraints creation and description etc are shown in this course.

In this course, you

1- Identify and apply timing arc information from a library, such as unateness, delays, and slew

2- Identify cell delays from a library and calculate output slew degradation

3- Use wire-load information to calculate net delays

4- Identify the properties of a clock, including period, edges, and slew, and calculate the duty cycle

5- Apply setup and hold checks to diagnose design violations 6- Identify timing path types to calculate slack values

7- Set environmental constraints, clocks constraints, and path exceptions

8- Constrain a design using SDC

9- Analyze reports to identify timing problems Course Agenda

1- Introduction to Static Timing Analysis

2- Understanding Cell Delay

3- Net Delay

4- Clocks

5- Timing Checks

6- Understanding Timing Paths

7- Introduction to SDC Constraints

8- Setting Timing Constraints

9- Setting Up the Database

10- Setting Timing Constraints

11- Setting Path Exceptions

12- Analyzing a Timing Report

13- Analyzing the Timing in a Design

14- Appendices

Timing Library Example

Latch-Based Designs