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An HDL design for sending data over Ethernet

License: MIT License

Tcl 12.73% SystemVerilog 64.04% Rust 23.23%

fpga-ethernet-udp's Introduction

I am a software engineer-in-training and physicist who creates solutions to diverse problems. Check out some of my current projects ↓

Photonics, signal processing, FPGA, and embedded systems in a cryogenic multiaxis range-resolved laser interferometer.
Studying language and compiler design to build the Fuyu programming language.
Customizing and tweaking my configs.

Create a usage example where values from the XADC are transmitted over Ethernet.

It might simplify things to separate the preamble from the rest of the frame, especially with respect to computing the CRC.

Although UDP checksums can be 0 for IPv4, is it smart to leave it as 0 or should it be computed?

The PHY clock requires a 50% duty cycle. The tolerance is that it must be between 40-60%.

The packet length does not take into account the 4 bytes from the counter.

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