A Verilog HDL model of the MOS 6502 CPU
Home Page: http://c-scape.nl/arlet/fpga/6502/
A Verilog HDL version of the old MOS 6502 CPU.
Note: the 6502 core assumes a synchronous memory. This means that valid data (DI) is expected on the cycle after valid address. This allows direct connection to (Xilinx) block RAMs. When using asynchronous memory, I suggest registering the address/control lines for glitchless output signals.
Have fun.
When 'reset' is active the write signal 'WE' is also active. This means some memory corruption during reset (but confined to the stack page)
These write cycles shouldn't be a problem unless the clock frequency is out of specs (but this can happen during PLL startups), and the boot memory is writable.
I think the real 6502 also modifies the stack pointer during resets but its R/W signal is forced high, disabling writes.
A possible patch is to change the following line...:
/*
always @*
case( state )
BRK0, // writing to stack or memory
BRK1,
BRK2,
JSR0,
JSR1,
PUSH1,
WRITE: WE = ~(reset|res); // (before it was: WE = 1;)
INDX3, // only if doing a STA, STX or STY
INDY3,
ABSX2,
ABS1,
ZPX1,
ZP0: WE = store;
default: WE = 0;
endcase
kallisti5@eris verilog-6502 :( $ verilator -sv -cc -Wno-fatal cpu.v
%Warning-WIDTH: ALU.v:57: Operator OR expects 9 bits on the LHS, but LHS's VARREF 'AI' generates 8 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: ALU.v:57: Operator OR expects 9 bits on the RHS, but RHS's VARREF 'BI' generates 8 bits.
%Warning-WIDTH: ALU.v:58: Operator AND expects 9 bits on the LHS, but LHS's VARREF 'AI' generates 8 bits.
%Warning-WIDTH: ALU.v:58: Operator AND expects 9 bits on the RHS, but RHS's VARREF 'BI' generates 8 bits.
%Warning-WIDTH: ALU.v:59: Operator XOR expects 9 bits on the LHS, but LHS's VARREF 'AI' generates 8 bits.
%Warning-WIDTH: ALU.v:59: Operator XOR expects 9 bits on the RHS, but RHS's VARREF 'BI' generates 8 bits.
%Warning-WIDTH: ALU.v:60: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS's VARREF 'AI' generates 8 bits.
%Warning-WIDTH: ALU.v:73: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'temp_logic' generates 9 bits.
%Warning-WIDTH: ALU.v:90: Operator ADD expects 5 bits on the RHS, but RHS's VARREF 'adder_CI' generates 1 bits.
%Warning-WIDTH: ALU.v:91: Operator ADD expects 5 bits on the RHS, but RHS's VARREF 'temp_HC' generates 1 bits.
%Warning-WIDTH: cpu.v:351: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'PC_inc' generates 1 bits.
%Warning-WIDTH: cpu.v:598: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '1'bx' generates 1 bits.
%Warning-CASEX: cpu.v:502: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:516: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:872: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEINCOMPLETE: cpu.v:872: Case values incompletely covered (example pattern 0x2)
%Warning-CASEINCOMPLETE: cpu.v:870: Case values incompletely covered (example pattern 0x32)
%Warning-CASEX: cpu.v:979: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEOVERLAP: cpu.v:988: Case values overlap (example pattern 0x88)
%Warning-CASEX: cpu.v:996: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1016: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEOVERLAP: cpu.v:1023: Case values overlap (example pattern 0x8e)
%Warning-CASEX: cpu.v:1037: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1049: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1060: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1071: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1079: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1089: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1098: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1107: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1117: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1128: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1137: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1147: Suggest casez (with ?'s) in place of casex (with X's)
%Warning-CASEX: cpu.v:1173: Suggest casez (with ?'s) in place of casex (with X's)
When trying to execute the BBC OS ROM v 1.2 I get a failure very early on.
D9CD LDA #&40 ;set NMI first instruction to RTI
D9CF STA &0D00 ;NMI ram start
This writes #&40 to &0000 rather than &0D00
I've tested this with Verilator. But seeing similar behaviour (unconfirmed) on Xilinx and Cyclone III.
kallisti5@eris verilog-6502 :) $ verilator -cc cpu.v
%Error: cpu.v:138: syntax error, unexpected bit, expecting IDENTIFIER or do or final
%Error: cpu.v:772: syntax error, unexpected ')', expecting "'{"
%Error: cpu.v:786: syntax error, unexpected ')', expecting "'{"
%Error: cpu.v:826: syntax error, unexpected ')', expecting "'{"
%Error: cpu.v:1175: syntax error, unexpected <=, expecting "'{"
%Error: cpu.v:1177: syntax error, unexpected <=, expecting "'{"
%Error: Exiting due to 6 error(s)
%Error: Command Failed /usr/local/bin/verilator_bin -cc cpu.v
kallisti5@eris verilog-6502 :) $ verilator -cc ALU.v
%Error: ALU.v:45: syntax error, unexpected logic, expecting IDENTIFIER or do or final
%Error: ALU.v:57: syntax error, unexpected '=', expecting "'{"
%Error: ALU.v:58: syntax error, unexpected '=', expecting "'{"
%Error: ALU.v:59: syntax error, unexpected '=', expecting "'{"
%Error: ALU.v:60: syntax error, unexpected '=', expecting "'{"
%Error: ALU.v:64: syntax error, unexpected '=', expecting "'{"
%Error: ALU.v:73: syntax error, unexpected ';', expecting "'{"
%Error: ALU.v:90: syntax error, unexpected '+', expecting "'{"
%Error: ALU.v:91: syntax error, unexpected '+', expecting "'{"
%Error: Exiting due to 9 error(s)
%Error: Command Failed /usr/local/bin/verilator_bin -cc ALU.v
Both the native GOWIN toolchain and yosys/apycula use the symbol ALU to designate internal logic units.
I just made it xALU in module definition and instantiation, but you may want something more creative...
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