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License: GNU General Public License v3.0
GPL v3 2D/3D graphics engine in verilog
License: GNU General Public License v3.0
Just leaving this here... gplgpu could move to open source tools. It seems like quite a few things build with iverilog.
Here is an example SCons script I threw together:
verilog_simulation = Builder(
action='iverilog -o $TARGET $VDLINCLUDES $SOURCES',
suffix='.vvp', src_suffix='.v')
env = Environment(BUILDERS = {'GenSim' : verilog_simulation})
env['VDLINCLUDES'] = "-I ./include"
generic_sources = [
'generic/gen_pipe.v'
]
math_sources = [
generic_sources,
'math/flt2int.v',
'math/flt_add_sub.v',
'math/flt_det.v',
'math/flt_frac_test.v',
'math/flt_fx_23p9.v',
'math/flt_fx_mult.v',
'math/flt_fx_uv.v',
'math/flt_int.v',
'math/flt_mult.v',
#'math/flt_recip_orig.v',
'math/log2_table.v',
'math/sv_log2.v',
'math/flt_add_sub_comb.v',
'math/flt_alu.v',
'math/flt_div.v',
'math/flt_fx1616_mult.v',
'math/flt_fx_24p8.v',
'math/flt_fx_rnd.v',
'math/flt_fx.v',
'math/flt_mult_comb.v',
'math/flt_recip_fast.v',
#'math/flt_recip.v',
#'math/real_log2_table.v'
]
env.GenSim('clk_gen/clk_gen.v')
env.GenSim('clk_switch/clk_switch.v')
env.GenSim('math/math', math_sources)
user@desktop hdl :) $ scons
scons: Reading SConscript files ...
scons: done reading SConscript files.
scons: Building targets ...
iverilog -o clk_gen/clk_gen.vvp -I ./include clk_gen/clk_gen.v
iverilog -o clk_switch/clk_switch.vvp -I ./include clk_switch/clk_switch.v
iverilog -o math/math.vvp -I ./include generic/gen_pipe.v math/flt2int.v math/flt_add_sub.v math/flt_det.v math/flt_frac_test.v math/flt_fx_23p9.v math/flt_fx_mult.v math/flt_fx_uv.v math/flt_int.v math/flt_mult.v math/log2_table.v math/sv_log2.v math/flt_add_sub_comb.v math/flt_alu.v math/flt_div.v math/flt_fx1616_mult.v math/flt_fx_24p8.v math/flt_fx_rnd.v math/flt_fx.v math/flt_mult_comb.v math/flt_recip_fast.v
scons: done building targets.
user@desktop hdl :) $ math/math.vvp
SORRY: math/sv_log2.v:62: $log() is not available in Icarus verilog.
user@desktop hdl :) $
I just wish I knew more about verilog and how these simulation files should fit together :-(
As the basic FPGA logic has been written, we should document current FPGA sizing and pin connections.
Hello,
I am a senior at CU Boulder. I was wondering if I could get in contact with you about a project I'm working on. This would make my project live up to my vision of it. Also, I'm sorry about your kickstarter:/
Ex1)we use the gplgpu with bridge IP (axi to pci-e)
Ex2) Can we join the gplgpu the EBI(External Bus Interface) of Soc?
Ex3)can we join between Soc and the gplgpu just as a software?
Hi
I don't know if someone is still looking into this, but... I've found a board with very reasonable price and I was thinking of giving a try...
Would it be possible? Would a Cyclone IV EP4CGX75 handle this GPU? Where should I start looking to make the port? Where to look at to make a VGA output? There is a driver for this? The 2D default driver could handle it?
I've saw the other thread where inform that the 3D engine (85K LE) would surpass this FPGA (75K LE), but maybe there is a way to make it less (resize to half?). Anyway if it could handle 2D would be good enough for a start.
I was also looking at other board, it is a Xilinx Kintex 7 XC7K325T, double the price but there is a lot more of resources to play with. But I'm only a hobbyist, would it be too much?
Either way, thank you very much for sharing this project!
Its hard to understand how i could help you, and where i could start.
Since you developing in GPLv3 please make your work public: open issues and branches.
Right now i absolutely have no idea how to contribute, which language you use and more.
Thanks.
Hey, thanks a lot for open sourcing this!
I noticed that you licence this code commercially, however you have no contributor agreement. Have you read the article on selling exceptions? You may need to ask your contributors to agree to let you sell.
I just wanted to point this out, so that no confusion arises.
Tim
I've seen quite a few complaints about the math $log call in the open source tools:
verilator -Mdir obj_release/math --cc -sv -Wno-fatal -I./include obj_release/math/flt2int.v obj_release/math/flt_add_sub.v obj_release/math/flt_det.v obj_release/math/flt_frac_test.v obj_release/math/flt_fx_23p9.v obj_release/math/flt_fx_mult.v obj_release/math/flt_fx_uv.v obj_release/math/flt_int.v obj_release/math/flt_mult.v obj_release/math/log2_table.v obj_release/math/sv_log2.v obj_release/math/flt_add_sub_comb.v obj_release/math/flt_alu.v obj_release/math/flt_div.v obj_release/math/flt_fx1616_mult.v obj_release/math/flt_fx_24p8.v obj_release/math/flt_fx_rnd.v obj_release/math/flt_fx.v obj_release/math/flt_mult_comb.v obj_release/math/flt_recip_fast.v generic/gen_pipe.v
%Error: obj_release/math/sv_log2.v:62: Unsupported or unknown PLI call: $log
%Warning-STMTDLY: obj_release/math/sv_log2.v:63: Unsupported: Ignoring delay on this delayed statement.
%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
Not sure if this is something that could be made more generic?
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