badboy1307 Goto Github PK

8bit_sar_adc

Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

adc_interface

Verilog ADC interface for adc128s022 found in De0 Nano

advanced_physical_design_using_openlane_sky130_workshop

analog-to-digital

Verilog for using an ADC to sample analog video and output to a digital display (VGA, HDMI, etc.)

awesome-sky130-ips

badboy1307

Config files for my GitHub profile.

bigpulp

RISC-V manycore accelerator for HERO, bigPULP hardware platform

cad-algorithms

This is the repo for submitting your CAD Algorithms

caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

caravel_carrier

Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.

clock-tree-synthesis-gui

A Graphical User Interface for data visualization for clock tree synthesis

congestion-map-builder-for-gcells

Builds a congestion map for guide files which gives the routes of various nets in the chip design. Clock tree topology for nets from DEF file.

cores-swerv-el2

SweRV EL2 Core

cores-swervolf

FuseSoC-based SoC for SweRV EH1

cpu

CPU design with SystemVerilog/UVM verification

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

datasciencecoursera

datasharing

The Leek group guide to data sharing

dffram

Standard Cell Library based Memory Compiler using DFF cells

django

dpll

A collection of phase locked loop (PLL) related projects

e203_hbirdv2

The Ultra-Low Power RISC-V Core

ecc-encryption-system

This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Elliptic Curve Cryptography. This project was implemented using a spartan 3 FPGA kit.

edalize

An abstraction library for interfacing EDA tools

educational-materials

Educational materials for RISC-V

f4pga

FOSS Flow For FPGA

fiduccia_mattheyses_algorithm_implemntation

Fiduccia Mattheyses Algorithm Implemntation in C++

floorplanning

EDA - a simulated annealing algorithm of floorplaning in IC design