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floorplanning-1

FPGA Floorplanning Project

forcedirectedalgorithm

fpgahdl_xilinx

(RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC products

freepdk-45nm

ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

gds3d

Fork from https://sourceforge.net/projects/gds3d

gds3d-1

GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation of the layout, where the user has full, real time control over the camera position and angle, much like in a 3D video game. An other repo (https://github.com/skuep/GDS3D) as the same source and add few improvement like compression with server/client process. This release add two major feature with are assembly and export 3D model for GMSH. Assembly: this mean it’s possible to merge multi GDS (with different technologies) I also try to improve net highlight.

genetic-algorithm

Genetic algorithm tutorial for Python

github-slideshow

A robot powered training repository :robot:

hummingbird

Hummingbird compiles trained ML models into tensor computation for faster inference.

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

improved-goggles

kernighan-lin

Implementation of Kernighan-Lin graph partitioning algorithm in Python

kl-algorithm

kronos

Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations

legendary-adventure

lf-building-a-risc-v-cpu-core

mcy

Mutation Cover with Yosys (MCY)

medium-article

Repository of code for Medium Article

mflowgen

mflowgen -- A Modular ASIC/FPGA Flow Generator

midicloro

MIDI clock generator and router

ml-for-beginners

12 weeks, 24 lessons, classic Machine Learning for all

my_projects

open-source-fpga-resource

A list of resources related to the open-source FPGA projects

openfasoc

Fully Open Source FASOC generators built on top of OpenROAD

openfpga

An Open-source FPGA IP Generator

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openlane__documentation

OpenLane Documentation

openlane_build_script

This script builds openlane and all its dependencies on an Ubuntu (only) System.