Comments (1)
This is what I've been always fighting with. Intel never bothered to create formal strict syntax rules for the instruction set and the syntax changes in time. Long time ago, the imm8
operand was completely undocumented. The manuals that this reference is based on (15 years back) say: D4 Ib (no mnemonic)
. That's why someone invented the AMX
mnemonic for arbitrary imm8
.
In the D40A AAM
, from the strict formal point of view, the 0A
is actually a "fixed immediate operand". I didn't want to introduce yet another operand type just because AAM
and AAD
so I went with sec_opcd
. This should be fine because the Intel manual merely says D40A AAM
, without any mention the 0A
part is actually an immediate value.
You're right, the newer manuals say D4 ib AAM imm8
and the reference should be updated now.
By the way, AAM imm8
doesn't make sense because the first letter A
stands for "ASCII", referring to the immediate value 0A
. When it's different from 0A
, the first letter should disappear. So it should be AM
, which is too short. That's why AMX
makes sense to me.
from x86reference.
Related Issues (16)
- No-operand version of FSUB is missing
- Error in Table "32/64-bit ModR/M Byte" HOT 1
- about avx HOT 4
- Document x87 instruction provenance HOT 2
- PALIGNR missing imm8 operand 3
- SIB Notes are wrong/misleading
- Mov Debug register possible wrong operand type HOT 1
- SFENCE requires sec_opcd HOT 4
- Add XBTS and IBTS instructions (80386 only)
- [Enhancement] Add JSON reference file HOT 1
- Missing Bit Manipulation Instruction Sets: ABM, BMI1, BMI2, and TBM HOT 1
- Relicense suggestion HOT 5
- Possible error in PUSH immediate HOT 1
- Opcode field for SETcc unnecessary HOT 1
- Redundant second opcode values instead of mod attribute HOT 9
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from x86reference.