ben-marshall / awesome-open-hardware-verification Goto Github PK

The following link regarding OpenHW Group Functional Verification Verification Strategy Document:
https://core-v-docs-verif-strat.readthedocs.io/en/latest/
does not work. There is 404 (not found) error for this page.

Please update the link.

Hi,

I'm developing some OSS VIP and tool.
Could you please add my works to your list?

• tvip-axi
  • Bus function model for AMBA AXI protocol
  • Written in SystemVerilog and UVM
  • https://github.com/taichi-ishitani/tvip-axi
  • License: Apache-2.0
• tvip-apb
  • Bus function model for AMBA APB protocol
  • Written in SystemVerilog and UVM
  • https://github.com/taichi-ishitani/tvip-apb
  • License: Apache-2.0
• RgGen
  • Code generator tool for CSR (configuration and status register)
    • Generating UVM RAL model from register map specification
  • Written in Ruby
  • https://github.com/rggen/rggen
  • License: MIT

Hi! I am new to this space and trying to learn more :) Thank you for putting together this great collection of tools!

I am looking for an open-source tool that can performance equivalence checking / verification between a C++ function and an RTL implementation of that function. Proprietary HLS tools have this built in but I was wondering if you knew of any open source versions that might suit these needs.

Thank you!

https://chipsalliance.org/workshops-meetings/

Nov 14/15th

Daniel Kroening and his team at Oxford Uni have developed a formal verif tool. I think it has support from the EU somehow.

From my experience the engine looks like it's probably very good, but the UI is basic and I have hit some issues compiling SV occasionally, It's the best free formal tool I've seen though.

Enhanced Bounded Model Checker, includes unbounded!
http://www.cprover.org/ebmc/