Topic: vhdl Goto Github

Some thing interesting about vhdl

👇 Here are 2393 public repositories matching this topic...

antonblanchard / microwatt

vhdl,A tiny Open POWER ISA softcore written in VHDL 2008

User: antonblanchard

vhdl processor openpower ppc64le

apertus-open-source-cinema / axiom-firmware

vhdl,AXIOM firmware (linux image, gateware and software tools)

Organization: apertus-open-source-cinema

apertus axiom-beta axiom-cameras boot camera firmware gateware hacktoberfest hardware linux openhardware qemu u-boot vhdl

ben-marshall / awesome-open-hardware-verification

vhdl,A List of Free and Open Source Hardware Verification Tools and Frameworks

User: ben-marshall

hardware verification vhdl verilog formal-verification constrained-random-verification python awesome awesome-list coverage

clash-lang / clash-compiler

vhdl,Haskell to VHDL/Verilog/SystemVerilog compiler

Organization: clash-lang

Home Page: https://clash-lang.org/

haskell hardware-description-language fpga vhdl verilog systemverilog asic

cocotb / cocotb

vhdl,cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Organization: cocotb

Home Page: https://www.cocotb.org

python vhdl verilog uvm verification test

degatecommunity / degate

vhdl,A modern and open-source cross-platform software for chips reverse engineering.

Organization: degatecommunity

Home Page: https://www.degate.org

verilog vlsi vhdl gui reverse-engineering security security-tools cybersecurity multi-platform chips cpp cross-platform

domipheus / rpu

vhdl,Basic RISC-V CPU implementation in VHDL.

User: domipheus

Home Page: http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-15-introducing-rpu/

fpga cpu vhdl risc-v riscv apache2-license

drom / awesome-hdl

vhdl,Hardware Description Languages

User: drom

awesome awesome-list hardware-description-language verilog vhdl hdl hacktoberfest

fabioperez / space-invaders-vhdl

vhdl,Space Invaders game implemented with VHDL

User: fabioperez

fpga games hardware vhdl

forflo / yodl

vhdl,A VHDL frontend for Yosys

User: forflo

vhdl yosys

ghdl / ghdl

vhdl,VHDL 2008/93/87 simulator

Organization: ghdl

vhdl ghdl simulator testbench compiler gcc llvm hardware hacktoberfest

gowtham1729 / image-processing

vhdl,Image Processing Toolbox in Verilog using Basys3 FPGA

User: gowtham1729

verilog verilog-hdl verilog-project vhdl python3 basys3 basys-board basys fpga pixel

hdl4fpga / hdl4fpga

vhdl,VHDL library 4 FPGAs

User: hdl4fpga

vhdl oscilloscope portable

howerj / bit-serial

vhdl,A bit-serial CPU written in VHDL, with a simulator written in C.

User: howerj

vhdl cpu bit-serial forth 16-bit 16-bit-cpu tiny 1bit

howerj / forth-cpu

vhdl,A Forth CPU and System on a Chip, based on the J1, written in VHDL

User: howerj

vhdl forth simulator target-board processor cpu c softcore fpga

im-tomu / fomu-workshop

vhdl,Support files for participating in a Fomu workshop

Organization: im-tomu

Home Page: https://workshop.fomu.im

fomu fomu-workshop vhdl verilog litex fpga riscv hdl chisel migen

jakubcabal / spi-fpga

vhdl,SPI master and SPI slave for FPGA written in VHDL

User: jakubcabal

spi-slave spi-master fpga vhdl spi controller spi-loopback spi-controller cyc1000 accelerometer

jeremiah-c-leary / vhdl-style-guide

vhdl,Style guide enforcement for VHDL

User: jeremiah-c-leary

beautify coding guide linting standard style styleguide vhdl

jofrfu / tinytpu

vhdl,Implementation of a Tensor Processing Unit for embedded systems and the IoT.

User: jofrfu

fpga fpga-accelerator tensorflow tensor tpu vhdl zynq xilinx vivado assembly

juliankemmerer / pipelinec

vhdl,A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

User: juliankemmerer

Home Page: https://github.com/JulianKemmerer/PipelineC/wiki

fpga hardware-description-language vhdl pipelines c python hardware hardware-description high-level-synthesis hls

kevinpt / symbolator

vhdl,HDL symbol generator

User: kevinpt

Home Page: https://kevinpt.github.io/symbolator

hdl vhdl verilog symbol

logisim-evolution / logisim-evolution

vhdl,Digital logic design tool and simulator

Organization: logisim-evolution

logisim-evolution education circuit circuits digital-circuit digital-circuits simulator logic digital-logic digital-logic-design

nic30 / hdlconvertor

vhdl,Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

User: nic30

antrl4 fpga parser python systemverilog systemverilog-parser verilog verilog-parser vhdl vhdl-parser

nic30 / hwt

vhdl,VHDL/Verilog/SystemC code generator, simulator API written in python/c++

User: nic30

codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl

nickg / nvc

vhdl,VHDL compiler and simulator

User: nickg

Home Page: https://www.nickg.me.uk/nvc/

vhdl simulator compiler fpga

nitram2342 / degate

vhdl,Open source software for chip reverse engineering.

User: nitram2342

Home Page: http://www.degate.org/

chip vlsi verilog vhdl visualization gui library image-processing image-recognition reverse-engineering

nuand / bladerf-wiphy

vhdl,bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

Organization: nuand

bladerf vhdl hdl rtl ofdm ofdm-wireless-communications dsss 80211

olofk / edalize

vhdl,An abstraction library for interfacing EDA tools

User: olofk

eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog

olofk / fusesoc

vhdl,Package manager and build abstraction tool for FPGA/ASIC development

User: olofk

python eda reuse package-manager fpga verilog vhdl

open-sdr / openwifi-hw

vhdl,open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Organization: open-sdr

fpga ofdm wi-fi zynq linux mac80211 csma dma verilog hls

osvvm / axi4

vhdl,AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

Organization: osvvm

osvvm axi4 axi4-lite axi4-stream verification vhdl vip verification-component tlm testbench

osvvm / osvvm

vhdl,OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

Organization: osvvm

verification-methodologies testbench coverage vhdl constrained-random simulation verification alerts memory memory-model

rggen / rggen

vhdl,Code generation tool for control and status registers

Organization: rggen

verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions

sergeykhbr / riscv_vhdl

vhdl,Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

User: sergeykhbr

Home Page: http://sergeykhbr.github.io/riscv_vhdl/

riscv soc vhdl simulator systemc qt cpu debugger

skordal / potato

vhdl,A simple RISC-V processor for use in FPGA designs.

User: skordal

processor risc-v vhdl

slaclab / surf

vhdl,A huge VHDL library for FPGA development

Organization: slaclab

asic firmware fpga hdl python vhdl

spinalhdl / spinalhdl

vhdl,Scala based HDL

Organization: spinalhdl

scala rtl vhdl verilog fpga

spinalhdl / vexriscv

vhdl,A FPGA friendly 32 bit RISC-V CPU implementation

Organization: spinalhdl

cpu fpga riscv soc softcore spinalhdl verilog vhdl

stnolting / captouch

vhdl,👇 Add capacitive touch buttons to any FPGA!

User: stnolting

vhdl capacitive-touch-sensor fpga button keypad fomu

stnolting / fpga_puf

vhdl,:key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

User: stnolting

authentication fingerprint fpga key-generation neorv32 puf security vhdl

stnolting / neo430

vhdl,:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

User: stnolting

vhdl fpga soft-core microcontroller msp430 gcc customizable processor soc system-on-chip

stnolting / neorv32

vhdl,:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

User: stnolting

Home Page: https://neorv32.org

risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip

stnolting / neotrng

vhdl,🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

User: stnolting

vhdl fpga trng random-number-generators random ring-oscillator entropy-source neorv32 cryptography entropy

suoto / hdl_checker

vhdl,Repurposing existing HDL tools to help writing better code

User: suoto

vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server

terostechnology / vscode-teroshdl

vhdl,VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Organization: terostechnology

Home Page: https://terostechnology.github.io/terosHDLdoc/

verilog vhdl systemverilog fpga

vhdl-ls / rust_hdl

vhdl,

Organization: vhdl-ls

vhdl language-server vhdl-parser vhdl-language-server parser rust-programming-language

vlsi-eda / poc

vhdl,IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Organization: vlsi-eda

Home Page: https://tu-dresden.de/ing/informatik/ti/vlsi

vhdl poc-library python simulation synthesis verification vlsi testbenches hardware-modules fpga