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DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 73.98% Verilog 22.32% Stata 1.82% Tcl 1.88%
ddr3 verilog systemverilog altera intel lattice xilinx testbenches fpga hdl

brianhg-ddr3-controller's Introduction

  • 👋 Hi, I’m @BrianHGinc
  • 👀 I’m interested in FPGA System Verilog HDL source code and microcontroler coding.
  • 🌱 I’m currently helping and offering free source code with embeded documentation.
  • 💞️ I’m looking to help those integrate my source code into their projects.
  • 📫 How to reach me here on github or at https://www.eevblog.com/forum/index.php as BrianHG in the FPGA section of the forum.

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brianhg-ddr3-controller's Issues

Deca Video Frame buffer example with your DDR3 controller

Hi Brian and congratulations on your awesome work!!!!

This is not really an issue, but just as we are developing cores for Deca board we just need a way to implement your DDR3 controller to allow a video frame buffer for most of the cores at https://github.com/DECAfpga to output a proper HDMI video with standard resolution to make it compatible with the majority of monitors.

If you have the expertise to do that, we would love to see that example of use!!!

The Arcade cores would be a perfect target as they do not require anything else but the Deca and a Keyboard.

Thanks again.

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