Topic: altera Goto Github
Some thing interesting about altera
Some thing interesting about altera
altera,FPGA mandelbrot accelerator via high speed/super speed USB
Organization: amaranth-farm
altera,DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
User: brianhginc
altera,Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)
User: delhatch
altera,Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.
User: delhatch
altera,24-bit Stereo Audio DAC for Raspberry Pi
User: dilshan
altera,Docs, design, firmware, and software for the Haasoscope
User: drandyhaas
Home Page: https://www.crowdsupply.com/andy-haas/haasoscope
altera,Projects and labs from the courses dictated in https://www.coursera.org/specializations/fpga-design. Projects are sometimes simulated, and implemented in either a MAX10-Lite or an Arrow MAX1000 board.-
User: fjpolo
altera,Tools for running FPGA vendor toolchains with Docker
User: halfmanhalftaco
altera,Stereo digital 2-way crossover filters processing I2S audio (16bit or 24bit) streams
User: har-in-air
altera,A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Organization: hdl-modules
Home Page: https://hdl-modules.com
altera,ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
User: hukenovs
altera,Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
User: hukenovs
altera,Verilog HDL implementation of the GOST 28147-89 β a Soviet and Russian government standard symmetric key block cipher
User: idoka
Home Page: http://idoka.ru/crypto-ip-core-gost-28147-89/
altera,Verilog HDL implementation of the GOST R34.12-2015 β a fresh Russian government standard symmetric key block cipher.
User: idoka
Home Page: http://idoka.ru/crypto-ip-core-gost-r3412-2015/
altera,MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.
User: idoka
Home Page: http://idoka.ru/verilog-ecc-generator/
altera,Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.
Organization: lombiq
altera,Expiremental Speech Recognition System using VHDL & MATLAB.
User: mohammedrashad
altera,fpga verilog risc-v rv32i cpu
User: nobotro
altera,All open source file and project for OpenFPGAduino project
Organization: openfpgaduino
Home Page: http://openfpgaduino.github.io
altera,Simple handmade open source mobile phone
User: orangeneko
altera,Demonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework
User: robseb
altera, SoCFPGA: Mapping HPS Peripherals, like IΒ²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
User: robseb
altera,Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide
User: robseb
Home Page: https://layers.openembedded.org/layerindex/branch/master/layer/meta-intelfpga/
altera,A 32-bit MIPS processor used Altera Quartus II with Verilog.
User: sevvalmehder
altera,Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
User: suoto
altera,DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.
User: thinkoco
altera,Altera JTAG UART wrapper for Bluespec
User: thotypous
altera,A Python module to interact with an Intel JTAG UART
User: tomverbeure
Home Page: https://pypi.org/project/intel_jtag_uart
altera,Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.
User: vignesh-raghavan
altera,IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische UniversitΓ€t Dresden, Germany
Organization: vlsi-eda
Home Page: https://tu-dresden.de/ing/informatik/ti/vlsi
altera,Matrix Multiplication in Hardware
User: voldemoriarty
altera,Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
Organization: wissance
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