Comments (2)
Ahh So these are from projects with chips from previous versions of the app.
understood.
from digital-logic-sim-ce.
Comp stands for "compatibility", it is a "transient" folder means that every chip that falls there should be moved elsewhere, infants the comp folder is disabled when it is empty.
If this is not the case let me know, maybe there is some problem there that should be investigated
from digital-logic-sim-ce.
Related Issues (20)
- Minor UX Improvements HOT 10
- A Travesty! (First bug encountered V0.39, yes I compiled it) HOT 8
- ctrl-z HOT 2
- disallow using chips that use the current chip `c` as a building block when editing `c` HOT 1
- 1Hz clock forgets its connections when compiled HOT 1
- Chips not saving properly when chip doesn't have input AND output. HOT 1
- Be compliant with Sebastian's community project guidelines
- Wires should be disconnected from IO pins when their bus type changes. HOT 1
- Edited chips do not load IO pin wire type correctly. HOT 1
- Allow direct pin bus modification HOT 2
- Key input
- BUSes reset to Simple when editing chips HOT 1
- Output pins do not update when changing input. HOT 9
- Make this repo a homebrew "tap" HOT 9
- FPS target gets reset on app startup HOT 1
- NOT gate without input don't work in chips
- Add tri-state buffers and buses HOT 1
- Macbook blocks application HOT 1
- Cannot delete wires unless I create a new one HOT 1
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