Comments (1)
Hi @y2k04 and welcome.
Thank you for the report; Once again, I can confirm I'm a bad programmer.
A PR fixing the problem would be nice, it should be quick to fix.
Else, just wait for me or any contributor to get a fix done.
from digital-logic-sim-ce.
Related Issues (20)
- Minor UX Improvements HOT 10
- A Travesty! (First bug encountered V0.39, yes I compiled it) HOT 8
- ctrl-z HOT 2
- disallow using chips that use the current chip `c` as a building block when editing `c` HOT 1
- 1Hz clock forgets its connections when compiled HOT 1
- Chips not saving properly when chip doesn't have input AND output. HOT 1
- Be compliant with Sebastian's community project guidelines
- "Comp" Folder disabled HOT 2
- Wires should be disconnected from IO pins when their bus type changes. HOT 1
- Edited chips do not load IO pin wire type correctly. HOT 1
- Allow direct pin bus modification HOT 2
- Key input
- BUSes reset to Simple when editing chips HOT 1
- Output pins do not update when changing input. HOT 9
- Make this repo a homebrew "tap" HOT 9
- NOT gate without input don't work in chips
- Add tri-state buffers and buses HOT 1
- Macbook blocks application HOT 1
- Cannot delete wires unless I create a new one HOT 1
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from digital-logic-sim-ce.