Comments (6)
I have the same issue as well. Besides, no feedback has returned from testbench (vvp --vp_test--
), despite there are lots of display functions in verilog testbench.
from caravel_user_project.
We're having the same trouble. When we try to run the command, $make verify-io_ports, we get the following error:
.../caravel_user_project/caravel/verilog/rtl/caravel_netlists.v:90: Include file mgmt_core_wrapper.v not found
from caravel_user_project.
This is quite a common error. There's a new tag mpw-5b
which should fix this. If you don't want to pull in those changes you can manually include the managment core by adding -I ../../../mgmt_core_wrapper/verilog/rtl
to the iverilog
command in the verilog/dv/io_ports/Makefile
but then there's also other errors if you do this.
I hope this helps
from caravel_user_project.
Thanks, that's worked for me!
This is quite a common error. There's a new tag
mpw-5b
which should fix this. If you don't want to pull in those changes you can manually include the managment core by adding-I ../../../mgmt_core_wrapper/verilog/rtl
to theiverilog
command in theverilog/dv/io_ports/Makefile
but then there's also other errors if you do this.I hope this helps
from caravel_user_project.
I switched the new tag mpw-5b
, however gate level simulation gives me this error iverilog: cannot open command file ../../caravel_user_project/mgmt_core_wrapper/verilog/includes/includes.gl.caravel_user_project for reading.
, even though RTL simulation run flawless. There is no such file in mgmt folder and I could not find it on the Internet. I only want to customize user project so that I do not want to add any external files to caravel or mgmt base folders.
from caravel_user_project.
Fixed in PR
from caravel_user_project.
Related Issues (20)
- update makefile with correct pdk commit HOT 1
- gfmpw-1: Makefile displays error with missing cocotb directory
- tag mpw-9e: referenced pdk missing sram maglefs
- gf180mcu SRAM macros causing illegal overlap HOT 1
- gfmpw-1 issues. HOT 2
- gfmpw-1 user_defines constants for bidirectional incorrect.
- gfmpw-1 outdated wrapper dimensions in docs
- gfmpw-1 dv issues HOT 1
- gfmpw1 run-precheck Makefile target uses -it, breaks github actions HOT 2
- LVS errors in the design HOT 1
- reg_debug_2 redefined warning
- Provide config.json file for synthesizing user_project_wrapper
- There is no signoff constraints file
- add the user_defines.v gpio defaults to the default includes to enable much faster simulation / testing
- analog power supply vdda1 and vssaa do not get connected during mixed signal designs HOT 4
- RTL-verification (sky130A) HOT 5
- Make target for running LVS and DRC standalone
- Using other Simulators instead of Iverilog
- Fix base_user_proj_example.sdc file for irq port constraints
- cocotb simulation not documented
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