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cs267-tutorials

Materials to help you with the cs267 homework.

custom-afl-instrumentation

A small example on how to use a custom coverage/progress metric for AFL. Based on the llvm_mode from AFL.

dank-formal

Experimental library for formal verification of Chisel modules using SymbiYosys

darjeeling-infuser

the infuser of the darjeeling project

darjeeling-jvm

git import of the embedded jvm from Delft University of Technology http://darjeeling.sourceforge.net

edsacjr-sim

ekiwi-scons-tools

Some scons tools that have accumulated over time, but are not good enough to be proposed to upstream.

ekiwi.github.io

engine-v

SoftCPU/SoC engine-V

essent

high-performance RTL simulator

etm

Manages access to microcontroller targets connected to our CI server.

etm-test

Playing around with the micro controller execution tracing.

ffi_benchmarks

firesim

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

firrtl

Flexible Intermediate Representation for RTL

firrtl-fuzzer

An attempt at a random generator for firrtl which could later be combined with the JQF fuzzer.

firrtl-gtksourceview

GtkSourceView language definition file for the Firrtl digital circuits IR.

firrtl-spec

The specification for the FIRRTL language

firrtl-uclid

fomu-workshop

Support files for participating in a Fomu workshop

fpgamacro

A Chisel3 package to describe verilog FPGA template and macro for hardened FPGA modules

gnome-builder

Builder is an IDE for GNOME

guarded_atomic_actions

hdmicore

HDMI core in Chisel HDL

hyperkernel

Fork of the hyperkernel source code: https://unsat.cs.washington.edu/papers/nelson-hyperkernel.pdf

icesugar-chisel

Chisel Examples for the iCESugar FPGA Board

ip-contributions

For contributions of Chisel IP to the chisel community.

iph

Optical Link University Project

irpy

LLVM IR -> Python compiler from the hyper kernel ecosystem (https://github.com/locore/hv6)

iuhr

RGB 7-Segment Display from LED Stripes