fpga-logi / logi-hard Goto Github PK

.../logi-hard/hdl/wishbone/peripherals/max7219_wb.vhd

trying to open project: logipi_face.xise

new download of logi-hard & logi-projects

via Google I found this file:
https://github.com/fpga-logi-dev/logi-hard/blob/master/hdl/wishbone/peripherals/max7219_wb.vhd
and copied in place

synthesis had many warnings but no errors.

Hi

In gpmc_wishbone_wrapper_aad.vhd I spotted a possible mistake but not sure if you meant to implement it that way.

In the gen_burst process isnt it wrong to increment the gpmc_counter if iob_oen and iob_wen are 0?

Should it not be an OR instead of AND as OEN and WEN will never be low at the same time
if ((iob_oen or iob_wen) = '0') then
gpmc_counter <= gpmc_counter + '1';

Thanks

Ilia

Hello JPiat,
I want to know about GPMC interface as I am newbie in BBB world. basically I am an FPGA Programmer and now I want to use BBB for my project. Initially I want to send some data from BBB to Logi-bone through GPMC. The FPGA recieves the data, save in SDRAM and send back to BBB. I have searched a lot about GPMC interface but could not find such material.
I have seen some projects (like SDRAM test, virtual components) in this list and got (very little) knowledge about how to configure GPMC bus. But for full understanding I need little help if you can.
Thanks
Zeeshan