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View Code? Open in Web Editor NEWThe 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track
The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track
Hello!I'm a green hand.I have some doubts about the training of my data set.After I have trained floating-point. Caffemodel with the solver.prototxt you gave me, I will use the DECENT tool to compress and quantify the network, and then compile it with DNNC.Get the result to replace your parameters that can be used?
And what you said about using fixed-point data in the training phase is not the same as this process?
I'm not sure. I'd appreciate it if you could answer@sl-zeng
I am wondering if the project support my ultra96 boards with PYNQ-image-v2.3?
Hi, hirayaku
I'm wondering if you can provide the dataset?
where is the devicetree.dtb
I am using the pynq_z1_v2.4.img, when burned, only BOOT.BIN image.ub in the card.
Hi,
I know in your sample code BATCH_SIZE = 5
as default.
But I wanna input only one image into SSD network,
so I changed BATCH_SIZE from 5 to 1 in preprocessing.py.
After doing so I executed SSD, there were no error.
but there were no detections in XML file, although it did work well
when BATCH_SIZE =5.
The result example is below:
BATCH_SIZE = 5:
<?xml version="1.0" encoding="utf-8"?>
<annotation>
<filename>0.jpg</filename>
<size>
<width>640</width>
<length>360</length>
</size>
<object>
<name>NotCare</name>
<bndbox>
<xmin>56</xmin>
<xmax>947</xmax>
<ymin>0</ymin>
<ymax>1080</ymax>
</bndbox>
</object>
</annotation>
BATCH_SIZE = 1:
<?xml version="1.0" encoding="utf-8"?>
<annotation>
<filename>0.jpg</filename>
<size>
<width>640</width>
<length>360</length>
</size>
<object>
<name>NotCare</name>
<bndbox>
<xmin>0</xmin>
<xmax>0</xmax>
<ymin>0</ymin>
<ymax>0</ymax>
</bndbox>
</object>
</annotation>
How do I input only one image at once??
If you have any comment, could you please how to do??
Best regards,
shinya321
Hi,
I ran the 'pynq_dpu_142m.tcl' script (folder 'block_design') in order to create the vivado project so that i could see the block design, but i got this error:
"The following IPs are not found in the IP Catalog:
deephi:user:axi2apb_top:1.0 user.org:user:dpu_top_wrapper:1.0"
How can i retrieve these IPs?
Thanks,
Sara
Hi,
Great repo and congratulate!
I have installed the DNNDK and finish the guide of compression and compilation.
I'm wonder which version of caffe you used to build your own ssd model?
And how can I train to get the float model? Can you provide the float.prototxt and the version of caffe?
Thanks
Hi,
I follow your tutorial to do ,but I find DNNDK has not supported pruning.
How are you doing the pruning?
Thanks.
Thank u for your great work!!
I am really interested in your SSD working on PYNQ board.
After building the environment following your README, step by step I execute your 'TGIIF.ipynb',
but I met an error as below:
> dpu_lib.dpu_initialize(c_lib_path) DPU InputSize : 338688 DPU OutputSize: 1058904 - - - - - - - - - - Illegal instruction
Where's wrong ?
Sorry to be poor English, it would be greatly appreciated if you could explain the details.
Best regards
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