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regds-logic-gate-extraction

A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.

rsfqlib

RSFQ cell library

scale-sim

simplesmithwatermancpp

A simple implementation of the smith-waterman algorithm (local alignment) in C++

smtattack

SMT Attack

spammpack

Sparse Approximate Matrix-Matrix Multiply Package

sparx

The SPARX family of lightweight block ciphers

superconducting-temporal-logic

Superconducting Accelerators Design Using Temporal Logic

swifold

Smith-Waterman Acceleration on Intel’s FPGA with OpenCL for Long DNA Sequences

usystolic-sim

A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.

vlsi_processor

A series of schematics, layouts, and test files used for the construction of an 8-bit register file and ALU. The layout was completed using the open-source Magic VLSI Layout Tool, and the schematic was constructed IRSIM. Layout-versus-schematic checks were completed using IRSIM, and the transient response was simulated using HSpice.

xnor-net-pytorch

PyTorch Implementation of XNOR-Net

xnor-network-operator

NO STL Version

zoo

Reference implementations of popular Binarized Neural Networks