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License: MIT License
A lot of the README files seem to have a "This is the readme" at the top of them. IE https://github.com/idea-fasoc/fasoc/tree/master/generators/adc-gen
The title should be the second line.
The page @ https://fasoc.engin.umich.edu/ says;
automatically synthesize “correct-by-construction” Verilog descriptions
There doesn't seem to be any definition about what you mean by “correct-by-construction” nor how your guarantee that result? Since it seems to be a core principle, I would have expected it to be clearly described + defined somewhere?
There are some small bugs on the check_env, I am getting errors for checking python version and other cadence tools. And there should be some check for the python libraries like numpy and so on. So just have that updated.
There is lot of information about potentially alternative flows in a doc at http://j.mp/openeda-diagram
The OpenRoad Project seems like it would also be a potentially good option.
The README file says the following;
Requirements: Python 3.6/3.7 (packages getopt, math, numpy, os, re, shutil, subprocess, sys, smtplib, datetime, logging, matplotlib). Python 3 is not supported.
I assume that last sentence should be Python 2 is not supported
?
You seem to have a whole bunch of generators at https://github.com/idea-fasoc/fasoc/tree/master/generators but very little documentation on what the generators do, how types of ranges they work on, how they are used, etc.
Might be a good idea to add a top level README.md to the generators directory and then a bit more information to each of the generators README files.
Based on what we have discussed, we will use the lower case letters for our final outputs.
Memory:
So, would you please change "Power" to "power" and AspectRatio to "aspect_ratio" in the mem-gen output json file?
PLL:
would you please change "Fnom_min" to "fnom_min", "Fnom_max" to "Fnom_max" and "aspect ratio" to "aspect_ratio" in the pll-gen output json file?
I was using calibre/2019.3_25 when "make gen_12lp_full" but it didn't generate ldo.pex.netlist which cause the post pex simulation not working. I changed to calibre/2020.3_38.22_aoj and solved the issue.
In the earlier releases of the PDK (e.g. 3af133706e554a740cfe60f21e773d9eaa41838c), the naming conventions are kept the same with the commercial release. However, in newer releases the names are modified to be consistent with the previous SKY130 OpenPDK.
In release 3af133706e554a740cfe60f21e773d9eaa41838c (2022-11-08)
The names are consistent with that in the commercial PDK release
MOS transistors are: nmos_3p3, pmos_6p0, …
Metal Names are: Metal1, Metal2, …
In newer OpenPDK releases:
MOS transistors are: nfet_03v3, pfet_06v0
Metal Names are: M1, M2, …
This discrepancy causes some issue when tools from different worlds are used together:
May I access private/cad?
As I am currently struggling to update config files and generate new Aux-cell using other PDKs, I was wondering if the source of the "AUXCELL_GEN" tool is available somewhere.
Further, I was wondering how could I extend the platform from tsmc65lp to my own PDKs(like tsmc130). And I would appreciate any help.
Best regards.
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