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View Code? Open in Web Editor NEWMIPS CPU implemented in Verilog
License: GNU General Public License v3.0
MIPS CPU implemented in Verilog
License: GNU General Public License v3.0
$0 should be zero at all time
Your code is pretty smart and concise.
Threre is something puzzling me in this file:
mips-cpu/test/cpu_tb.v
cpu#(.NMEM(
NUM_IM_DATA), .IM_DATA(
IM_DATA_FILE))
mips1(.clk(clk));
What are the first macro for? I can not figure it out, I can't find where IM_DATA_FILE is defined, either.
I would appreciate if I could get your help.
for these instrucitons,
20080001
08000004
00000000
21080100
21080001
the first iterm is pc ,which seems is not exactly right,
the target address is 00000010 , there are two of them
/* If an operation in stage 4 (MEM) loads from memory (e.g. lw)
* and the operation in stage 3 (EX) depends on this value,
* a stall must be performed. The memory read cannot
* be forwarded because memory access is too slow. It can
* be forwarded from stage 5 (WB) after a stall.
*
* lw $1, 16($10) ; I-type, rt_s3 = $1, memread_s3 = 1
* sw $1, 32($12) ; I-type, rt_s2 = $1, memread_s2 = 0
*
* lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1
* sw $2, 32($1) ; I-type, rt_s2 = $2, rs_s2 = $1, memread_s2 = 0
*
* lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1
* add $2, $1, $1 ; R-type, rs_s2 = $1, rt_s2 = $1, memread_s2 = 0
*/
always @(*) begin
if (memread_s3 == 1'b1 && ((rt == rt_s3) || (rs == rt_s3)) ) begin
stall_s1_s2 <= 1'b1; // perform a stall
end else
stall_s1_s2 <= 1'b0; // no stall
end
I cannot understand this, can someone help.
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