liangkangnan / tinyriscv Goto Github PK
View Code? Open in Web Editor NEWA very simple and easy to understand RISC-V core.
License: Apache License 2.0
A very simple and easy to understand RISC-V core.
License: Apache License 2.0
RTL文件中的ROM和RAM两个模块是一样的,为什么不删除一个。这样在顶层就直接调用两次就可以了。
而且ROM的是只读的吧?
请问下如何跑coremark,能否提供下步骤说明。
强烈支持此项目,我也是嵌入式工程师,正在学习RISC-V中,因方便自己学习制作了开源的iCESugar开发板
https://github.com/wuxx/icesugar
可以使用完全开源的工具链(yosys & nextpnr & icestorm)在Linux下开发,能否考虑移植tinyriscv到iCESugar上运行呢
用cmsis-dap仿真器连接的时候,出现这个报错,连接线和引脚约束检查好几遍了,还是没找到问题,有大佬知道咋解决吗
F:\tinyriscv\tools\openocd>openocd.exe -f tinyriscv.cfg
Open On-Chip Debugger 0.10.0+dev-00914-g4cb81306a-dirty (2020-01-28-21:35)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : CMSIS-DAP: SWD Supported
Info : CMSIS-DAP: JTAG Supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (JTAG)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : clock speed 1000 kHz
Info : cmsis-dap JTAG TLR_RESET
Info : cmsis-dap JTAG TLR_RESET
Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: riscv.cpu: IR capture error; saw 0x1f not 0x01
Info : cmsis-dap JTAG TLR_RESET
Warn : Bypassing JTAG setup events due to errors
Error: dtmcontrol is 0. Check JTAG connectivity/board power.
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet
作者您好,我按照您的教程跑完了coremark和uart、timer、gpio所有外设正常,config.h的配置也是您的工程,就是freertos未跑成功,LED未翻转,未设置SIMULATION宏定义,请问还有什么地方需要设置吗?
您的外设每个都是256M,25T的资源有限,我在quartus中选择10lp中最多资源的(比35t多很多)也无法通过编译,我不理解您怎么通过编译的,外设的大小可以控制吗
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